| Message ID | 20230726074049.19505-2-jason.chien@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add Zihintntl extension ISA string to DTS | expand |
Ping This patch seems to be ignored. patch link: https://lore.kernel.org/qemu-devel/20230726074049.19505-2-jason.chien@sifive.com/ On Wed, Jul 26, 2023 at 3:41 PM Jason Chien <jason.chien@sifive.com> wrote: > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > processors that will run rich OS stacks from standard binary OS > distributions and with a substantial number of third-party binary user > applications that will be supported over a considerable length of time > in the field. > > The chapter 4 of the unprivileged spec introduces the Zihintntl extension > and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose > purpose is to enable application and operating system portability across > different implementations. Thus the DTS should contain the Zihintntl ISA > string in order to pass to software. > > The unprivileged spec states: > Like any HINTs, these instructions may be freely ignored. Hence, although > they are described in terms of cache-based memory hierarchies, they do not > mandate the provision of caches. > > These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2, > which QEMU already supports, and QEMU does not emulate cache. Therefore > these instructions can be considered as a no-op, and we only need to add > a new property for the Zihintntl extension. > > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Signed-off-by: Jason Chien <jason.chien@sifive.com> > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 921c19e6cd..a49e934b41 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -87,6 +87,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), > + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > @@ -1763,6 +1764,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true), > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), > DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 2bd9510ba3..518686eaa3 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -66,6 +66,7 @@ struct RISCVCPUConfig { > bool ext_icbom; > bool ext_icboz; > bool ext_zicond; > + bool ext_zihintntl; > bool ext_zihintpause; > bool ext_smstateen; > bool ext_sstc; > -- > 2.17.1 > >
On Wed, Jul 26, 2023 at 3:42 AM Jason Chien <jason.chien@sifive.com> wrote: > > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > processors that will run rich OS stacks from standard binary OS > distributions and with a substantial number of third-party binary user > applications that will be supported over a considerable length of time > in the field. > > The chapter 4 of the unprivileged spec introduces the Zihintntl extension > and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose > purpose is to enable application and operating system portability across > different implementations. Thus the DTS should contain the Zihintntl ISA > string in order to pass to software. > > The unprivileged spec states: > Like any HINTs, these instructions may be freely ignored. Hence, although > they are described in terms of cache-based memory hierarchies, they do not > mandate the provision of caches. > > These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2, > which QEMU already supports, and QEMU does not emulate cache. Therefore > these instructions can be considered as a no-op, and we only need to add > a new property for the Zihintntl extension. > > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Signed-off-by: Jason Chien <jason.chien@sifive.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 921c19e6cd..a49e934b41 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -87,6 +87,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), > + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > @@ -1763,6 +1764,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true), > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), > DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 2bd9510ba3..518686eaa3 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -66,6 +66,7 @@ struct RISCVCPUConfig { > bool ext_icbom; > bool ext_icboz; > bool ext_zicond; > + bool ext_zihintntl; > bool ext_zihintpause; > bool ext_smstateen; > bool ext_sstc; > -- > 2.17.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 921c19e6cd..a49e934b41 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -87,6 +87,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), @@ -1763,6 +1764,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..518686eaa3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -66,6 +66,7 @@ struct RISCVCPUConfig { bool ext_icbom; bool ext_icboz; bool ext_zicond; + bool ext_zihintntl; bool ext_zihintpause; bool ext_smstateen; bool ext_sstc;