diff mbox series

[1/2] hw/intc: Fix upper/lower mtime write calculation

Message ID 20230728082502.26439-1-jason.chien@sifive.com (mailing list archive)
State New, archived
Headers show
Series [1/2] hw/intc: Fix upper/lower mtime write calculation | expand

Commit Message

Jason Chien July 28, 2023, 8:24 a.m. UTC 
When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
---
 hw/intc/riscv_aclint.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Jason Chien Aug. 8, 2023, 6:41 p.m. UTC | #1 
Hi,
The patch seems to be ignored. I am not sure who to ping. Could someone
please review this patch? Thank you!
patch link:
https://lore.kernel.org/qemu-devel/20230728082502.26439-1-jason.chien@sifive.com/

On Fri, Jul 28, 2023 at 4:25 PM Jason Chien <jason.chien@sifive.com> wrote:

> When writing the upper mtime, we should keep the original lower mtime
> whose value is given by cpu_riscv_read_rtc() instead of
> cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
>
> Signed-off-by: Jason Chien <jason.chien@sifive.com>
> ---
>  hw/intc/riscv_aclint.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index b466a6abaf..bf77e29a70 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -208,11 +208,12 @@ static void riscv_aclint_mtimer_write(void *opaque,
> hwaddr addr,
>          return;
>      } else if (addr == mtimer->time_base || addr == mtimer->time_base +
> 4) {
>          uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
> +        uint64_t rtc = cpu_riscv_read_rtc(mtimer);
>
>          if (addr == mtimer->time_base) {
>              if (size == 4) {
>                  /* time_lo for RV32/RV64 */
> -                mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) -
> rtc_r;
> +                mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) -
> rtc_r;
>              } else {
>                  /* time for RV64 */
>                  mtimer->time_delta = value - rtc_r;
> @@ -220,7 +221,7 @@ static void riscv_aclint_mtimer_write(void *opaque,
> hwaddr addr,
>          } else {
>              if (size == 4) {
>                  /* time_hi for RV32/RV64 */
> -                mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF))
> - rtc_r;
> +                mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) -
> rtc_r;
>              } else {
>                  qemu_log_mask(LOG_GUEST_ERROR,
>                                "aclint-mtimer: invalid time_hi write:
> %08x",
> --
> 2.17.1
>
>
Alistair Francis Aug. 10, 2023, 6:23 p.m. UTC | #2 
On Fri, Jul 28, 2023 at 5:13 AM Jason Chien <jason.chien@sifive.com> wrote:
>
> When writing the upper mtime, we should keep the original lower mtime
> whose value is given by cpu_riscv_read_rtc() instead of
> cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
>
> Signed-off-by: Jason Chien <jason.chien@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/intc/riscv_aclint.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index b466a6abaf..bf77e29a70 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -208,11 +208,12 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
>          return;
>      } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
>          uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
> +        uint64_t rtc = cpu_riscv_read_rtc(mtimer);
>
>          if (addr == mtimer->time_base) {
>              if (size == 4) {
>                  /* time_lo for RV32/RV64 */
> -                mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
> +                mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
>              } else {
>                  /* time for RV64 */
>                  mtimer->time_delta = value - rtc_r;
> @@ -220,7 +221,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
>          } else {
>              if (size == 4) {
>                  /* time_hi for RV32/RV64 */
> -                mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
> +                mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;
>              } else {
>                  qemu_log_mask(LOG_GUEST_ERROR,
>                                "aclint-mtimer: invalid time_hi write: %08x",
> --
> 2.17.1
>
>
diff mbox series

Patch

diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index b466a6abaf..bf77e29a70 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -208,11 +208,12 @@  static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
         return;
     } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
         uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
+        uint64_t rtc = cpu_riscv_read_rtc(mtimer);
 
         if (addr == mtimer->time_base) {
             if (size == 4) {
                 /* time_lo for RV32/RV64 */
-                mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
+                mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
             } else {
                 /* time for RV64 */
                 mtimer->time_delta = value - rtc_r;
@@ -220,7 +221,7 @@  static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
         } else {
             if (size == 4) {
                 /* time_hi for RV32/RV64 */
-                mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
+                mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r;
             } else {
                 qemu_log_mask(LOG_GUEST_ERROR,
                               "aclint-mtimer: invalid time_hi write: %08x",