@@ -34,9 +34,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
int exception = cs->exception_index;
env->epcr = env->pc;
- if (exception == EXCP_SYSCALL) {
- env->epcr += 4;
- }
+
/* When we have an illegal instruction the error effective address
shall be set to the illegal instruction address. */
if (exception == EXCP_ILLEGAL) {
@@ -63,6 +61,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->epcr -= 4;
} else {
env->sr &= ~SR_DSX;
+ if (exception == EXCP_SYSCALL || exception == EXCP_FPE) {
+ env->epcr += 4;
+ }
}
if (exception > 0 && exception < EXCP_NR) {
The architecture specification calls for the EPCR to be set to "Address of next not executed instruction" when there is a floating point exception (FPE). This was not being done, so fix it by using the same pattern as syscall. Also, we move this logic down to be done for instructions not in the delay slot as called for by the architecture manual. Without this patch FPU exceptions will loop, as the exception handling will always return back to the failed floating point instruction. This was not noticed in earlier testing because: 1. The compiler usually generates code which clobbers the input operand such as: lf.div.s r19,r17,r19 2. The target will store the operation output before to the register before handling the exception. So an operation such as: float a = 100.0f; float b = 0.0f; float c = a / b; /* lf.div.s r19,r17,r19 */ Will first execute: 100 / 0 -> Store inf to c (r19) -> triggering divide by zero exception -> handle and return Then it will execute: 100 / inf -> Store 0 to c (no exception) To confirm the looping behavior and the fix I used the following: float fpu_div(float a, float b) { float c; asm volatile("lf.div.s %0, %1, %2" : "+r" (c) : "r" (a), "r" (b)); return c; } Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> --- target/openrisc/interrupt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)