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[1/5] target/hppa: Add missing PL1 and PL2 priviledge levels

Message ID 20230824210434.151971-2-deller@kernel.org (mailing list archive)
State New, archived
Headers show
Series target/hppa: Clean up conversion from/to MMU index and priviledge level | expand

Commit Message

Helge Deller Aug. 24, 2023, 9:04 p.m. UTC 
From: Helge Deller <deller@gmx.de>

The hppa CPU has 4 priviledge levels (0-3).
Mention the missing PL1 and PL2 levels, although the Linux kernel
uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.

Signed-off-by: Helge Deller <deller@gmx.de>
---
 target/hppa/cpu.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Philippe Mathieu-Daudé Aug. 25, 2023, 7:11 a.m. UTC | #1 
On 24/8/23 23:04, deller@kernel.org wrote:
> From: Helge Deller <deller@gmx.de>
> 
> The hppa CPU has 4 priviledge levels (0-3).
> Mention the missing PL1 and PL2 levels, although the Linux kernel
> uses only 0 (KERNEL) and 3 (USER). Not sure about HP-UX.
> 
> Signed-off-by: Helge Deller <deller@gmx.de>
> ---
>   target/hppa/cpu.h | 3 +++
>   1 file changed, 3 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 75c5c0ccf7..6c5b0e67c8 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -31,8 +31,11 @@ 
 #define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
 
 #define MMU_KERNEL_IDX   0
+#define MMU_PL1_IDX      1
+#define MMU_PL2_IDX      2
 #define MMU_USER_IDX     3
 #define MMU_PHYS_IDX     4
+
 #define TARGET_INSN_START_EXTRA_WORDS 1
 
 /* Hardware exceptions, interrupts, faults, and traps.  */