diff mbox series

[3/5] target/hppa: Do not use hardcoded value for tlb_flush_*()

Message ID 20230824210434.151971-4-deller@kernel.org (mailing list archive)
State New, archived
Headers show
Series target/hppa: Clean up conversion from/to MMU index and priviledge level | expand

Commit Message

Helge Deller Aug. 24, 2023, 9:04 p.m. UTC
From: Helge Deller <deller@gmx.de>

Avoid using hardcoded values when calling the tlb_flush*() functions.
Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
Skip flushing the MMU for physical addresses.

Signed-off-by: Helge Deller <deller@gmx.de>
---
 target/hppa/cpu.h        | 5 +++++
 target/hppa/helper.c     | 2 +-
 target/hppa/mem_helper.c | 7 +++----
 3 files changed, 9 insertions(+), 5 deletions(-)

Comments

Philippe Mathieu-Daudé Aug. 25, 2023, 7:14 a.m. UTC | #1
On 24/8/23 23:04, deller@kernel.org wrote:
> From: Helge Deller <deller@gmx.de>
> 
> Avoid using hardcoded values when calling the tlb_flush*() functions.
> Instead define the correct mask (HPPA_MMU_FLUSH_MASK) and use it.
> Skip flushing the MMU for physical addresses.

Alternatively:

   Instead, define and use HPPA_MMU_FLUSH_MASK (keeping the current
   behavior, which doesn't flush the physical address MMU).

> 
> Signed-off-by: Helge Deller <deller@gmx.de>
> ---
>   target/hppa/cpu.h        | 5 +++++
>   target/hppa/helper.c     | 2 +-
>   target/hppa/mem_helper.c | 7 +++----
>   3 files changed, 9 insertions(+), 5 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 50b513f0ea..6623712644 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -41,6 +41,11 @@ 
 
 #define TARGET_INSN_START_EXTRA_WORDS 1
 
+/* No need to flush MMU_PHYS_IDX  */
+#define HPPA_MMU_FLUSH_MASK                             \
+        (1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX |       \
+         1 << MMU_PL2_IDX    | 1 << MMU_USER_IDX)
+
 /* Hardware exceptions, interrupts, faults, and traps.  */
 #define EXCP_HPMC                1  /* high priority machine check */
 #define EXCP_POWER_FAIL          2
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 74b8747083..a8d3f456ee 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -71,7 +71,7 @@  void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
     /* If PSW_P changes, it affects how we translate addresses.  */
     if ((psw ^ old_psw) & PSW_P) {
 #ifndef CONFIG_USER_ONLY
-        tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+        tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
 #endif
     }
 }
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 5046cc8f9d..6f04c101dd 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -50,8 +50,7 @@  static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
     trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
 
     for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
-        /* Do not flush MMU_PHYS_IDX.  */
-        tlb_flush_page_by_mmuidx(cs, addr, 0xf);
+        tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK);
     }
 
     memset(ent, 0, sizeof(*ent));
@@ -335,13 +334,13 @@  void HELPER(ptlbe)(CPUHPPAState *env)
 {
     trace_hppa_tlb_ptlbe(env);
     memset(env->tlb, 0, sizeof(env->tlb));
-    tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+    tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
 }
 
 void cpu_hppa_change_prot_id(CPUHPPAState *env)
 {
     if (env->psw & PSW_P) {
-        tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+        tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
     }
 }