@@ -41,6 +41,11 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* No need to flush MMU_PHYS_IDX */
+#define HPPA_MMU_FLUSH_MASK \
+ (1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX | \
+ 1 << MMU_PL2_IDX | 1 << MMU_USER_IDX)
+
/* Hardware exceptions, interrupts, faults, and traps. */
#define EXCP_HPMC 1 /* high priority machine check */
#define EXCP_POWER_FAIL 2
@@ -71,7 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
/* If PSW_P changes, it affects how we translate addresses. */
if ((psw ^ old_psw) & PSW_P) {
#ifndef CONFIG_USER_ONLY
- tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
#endif
}
}
@@ -50,8 +50,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
- /* Do not flush MMU_PHYS_IDX. */
- tlb_flush_page_by_mmuidx(cs, addr, 0xf);
+ tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK);
}
memset(ent, 0, sizeof(*ent));
@@ -335,13 +334,13 @@ void HELPER(ptlbe)(CPUHPPAState *env)
{
trace_hppa_tlb_ptlbe(env);
memset(env->tlb, 0, sizeof(env->tlb));
- tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
}
void cpu_hppa_change_prot_id(CPUHPPAState *env)
{
if (env->psw & PSW_P) {
- tlb_flush_by_mmuidx(env_cpu(env), 0xf);
+ tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
}
}