[PULL,v3,05/16] target/tricore: Clarify special case for FTOUZ insn

Commit Message

Bastian Koppelmann Sept. 29, 2023, 6:39 a.m. UTC

this is not something other ISAs do, so clarify it with a comment.

Reviewed-by: Richard Henderson <[e-mail]>
Signed-off-by: Bastian Koppelmann <[e-mail]>
Message-ID: <[e-mail]>
---
 target/tricore/fpu_helper.c | 5 +++++
 1 file changed, 5 insertions(+)

Patch

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3aefeb776e..d0c474c5f3 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -475,6 +475,11 @@  uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
         if (float32_is_any_nan(f_arg)) {
             result = 0;
         }
+    /*
+     * we need to check arg < 0.0 before rounding as TriCore needs to raise
+     * float_flag_invalid as well. For instance, when we have a negative
+     * exponent and sign, softfloat would only raise float_flat_inexact.
+     */
     } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
         flags = float_flag_invalid;
         result = 0;