Message ID | 20231003052345.199725-1-tong.ho@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | xlnx-bbram: hw/nvram: Remove deprecated device reset | expand |
Hi Tong, On 3/10/23 07:23, Tong Ho wrote: > This change implements the ResettableClass interface for the device. > > Signed-off-by: Tong Ho <tong.ho@amd.com> > --- > hw/nvram/xlnx-bbram.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Since you did this one, do you mind updating the other Xilinx devices? $ git grep -F -- '->reset = ' hw/*/*xlnx* hw/display/xlnx_dp.c:1399: dc->reset = xlnx_dp_reset; hw/dma/xlnx-zdma.c:827: dc->reset = zdma_reset; hw/dma/xlnx-zynq-devcfg.c:387: dc->reset = xlnx_zynq_devcfg_reset; hw/dma/xlnx_csu_dma.c:714: dc->reset = xlnx_csu_dma_reset; hw/dma/xlnx_dpdma.c:601: dc->reset = xlnx_dpdma_reset; hw/intc/xlnx-pmu-iomod-intc.c:539: dc->reset = xlnx_pmu_io_intc_reset; hw/intc/xlnx-zynqmp-ipi.c:362: dc->reset = xlnx_zynqmp_ipi_reset; hw/misc/xlnx-versal-cfu.c:498: dc->reset = cfu_apb_reset; hw/nvram/xlnx-bbram.c:526: dc->reset = bbram_ctrl_reset; hw/nvram/xlnx-versal-efuse-ctrl.c:753: dc->reset = efuse_ctrl_reset; hw/nvram/xlnx-zynqmp-efuse.c:841: dc->reset = zynqmp_efuse_reset; hw/rtc/xlnx-zynqmp-rtc.c:258: dc->reset = rtc_reset; hw/ssi/xlnx-versal-ospi.c:1833: dc->reset = xlnx_versal_ospi_reset;
Hi Philippe, Thanks for the review. The rest is in the pipeline. Regards, Tong Ho
On Tue, 3 Oct 2023 at 06:23, Tong Ho <tong.ho@amd.com> wrote: > > This change implements the ResettableClass interface for the device. > > Signed-off-by: Tong Ho <tong.ho@amd.com> > --- > hw/nvram/xlnx-bbram.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) Applied to target-arm.next, thanks. -- PMM
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c index c6b484cc85..e18e7770e1 100644 --- a/hw/nvram/xlnx-bbram.c +++ b/hw/nvram/xlnx-bbram.c @@ -2,6 +2,7 @@ * QEMU model of the Xilinx BBRAM Battery Backed RAM * * Copyright (c) 2014-2021 Xilinx Inc. + * Copyright (c) 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -416,9 +417,9 @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = { } }; -static void bbram_ctrl_reset(DeviceState *dev) +static void bbram_ctrl_reset_hold(Object *obj) { - XlnxBBRam *s = XLNX_BBRAM(dev); + XlnxBBRam *s = XLNX_BBRAM(obj); unsigned int i; for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { @@ -522,8 +523,9 @@ static Property bbram_ctrl_props[] = { static void bbram_ctrl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); - dc->reset = bbram_ctrl_reset; + rc->phases.hold = bbram_ctrl_reset_hold; dc->realize = bbram_ctrl_realize; dc->vmsd = &vmstate_bbram_ctrl; device_class_set_props(dc, bbram_ctrl_props);
This change implements the ResettableClass interface for the device. Signed-off-by: Tong Ho <tong.ho@amd.com> --- hw/nvram/xlnx-bbram.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)