From patchwork Thu Oct 5 22:22:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13410851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E18AE92FC9 for ; Thu, 5 Oct 2023 22:23:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qoWk7-0005Iz-Bg; Thu, 05 Oct 2023 18:22:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qoWk4-0005Gy-AQ for qemu-devel@nongnu.org; Thu, 05 Oct 2023 18:22:49 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qoWjz-0008D6-M6 for qemu-devel@nongnu.org; Thu, 05 Oct 2023 18:22:46 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 395Lwoi2025233; Thu, 5 Oct 2023 22:22:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=bYKLdQ36pxGKUGZpYELuCj+IOcsB2Gl3uqwu9hQPGDw=; b=BvfHcT85hefgU1uQFRankIX0jClKFCP3z32BTBHrc81nimcwIJMo5Xz+tp0d2SWSWr98 wz3vgQpRr2pXtmZwWdfKZRTg4j4jNvk4bVOnFe2JPWLgq+f61bt2kPvsQt03relKDjHJ 2XtQUuMlvRmAkgxvlkdkEcEm/y2KCleRNYK8FJLzcWGbD+2309F02+0kCs/Fuu//5nkn zIh+HhhFUbb9hxBwaauv5FakkhExcsuTP4uYq+4kFNi7HRo/VZirW0dmmNXkmWZbHlTt dD3ttj/fZ9NsVGuklSuAdt0ymJDXUFnD3ZMI/uqYzhrDxwjwRn6llPxVATrv5BhBNEUL Gw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3th8ck433f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Oct 2023 22:22:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 395MMVUY016763 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Oct 2023 22:22:31 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 5 Oct 2023 15:22:30 -0700 From: Brian Cain To: CC: , , , , , , , , , , Subject: [PATCH v2 2/3] target/hexagon: fix some occurrences of -Wshadow=local Date: Thu, 5 Oct 2023 15:22:05 -0700 Message-ID: <20231005222206.2784853-3-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005222206.2784853-1-bcain@quicinc.com> References: <20231005222206.2784853-1-bcain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rPYTyYLJHaj_N4A2XWf64G7G9ORxf4DH X-Proofpoint-ORIG-GUID: rPYTyYLJHaj_N4A2XWf64G7G9ORxf4DH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_17,2023-10-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 impostorscore=0 malwarescore=0 mlxlogscore=522 adultscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050169 Received-SPF: pass client-ip=205.220.168.131; envelope-from=bcain@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()` are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of ‘i’ shadows a previous local [-Werror=shadow=compatible-local] 205 | for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of ‘ra’ shadows a previous local [-Werror=shadow=compatible-local] 204 | uintptr_t ra = GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro ‘SCATTER_OP_WRITE_TO_MEM’ 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra = GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson --- target/hexagon/imported/alu.idef | 6 +++--- target/hexagon/mmvec/macros.h | 6 +++--- target/hexagon/op_helper.c | 9 +++------ target/hexagon/translate.c | 9 ++++----- 4 files changed, 13 insertions(+), 17 deletions(-) diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef index 12d2aac5d4..b855676989 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -1142,9 +1142,9 @@ Q6INSN(A4_cround_rr,"Rd32=cround(Rs32,Rt32)",ATTRIBS(),"Convergent Round", {RdV tmp128 = fSHIFTR128(tmp128, SHIFT);\ DST = fCAST16S_8S(tmp128);\ } else {\ - size16s_t rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \ - size16s_t src_128 = fCAST8S_16S(SRC); \ - size16s_t tmp128 = fADD128(src_128, rndbit_128);\ + rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \ + src_128 = fCAST8S_16S(SRC); \ + tmp128 = fADD128(src_128, rndbit_128);\ tmp128 = fSHIFTR128(tmp128, SHIFT);\ DST = fCAST16S_8S(tmp128);\ } diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index a655634fd1..728a63d35f 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -201,14 +201,14 @@ } while (0) #define SCATTER_OP_WRITE_TO_MEM(TYPE) \ do { \ - uintptr_t ra = GETPC(); \ + uintptr_t ra_ = GETPC(); \ for (int i = 0; i < sizeof(MMVector); i += sizeof(TYPE)) { \ if (test_bit(i, env->vtcm_log.mask)) { \ TYPE dst = 0; \ TYPE inc = 0; \ for (int j = 0; j < sizeof(TYPE); j++) { \ uint8_t val; \ - val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra); \ + val = cpu_ldub_data_ra(env, env->vtcm_log.va[i + j], ra_); \ dst |= val << (8 * j); \ inc |= env->vtcm_log.data.ub[j + i] << (8 * j); \ clear_bit(j + i, env->vtcm_log.mask); \ @@ -217,7 +217,7 @@ dst += inc; \ for (int j = 0; j < sizeof(TYPE); j++) { \ cpu_stb_data_ra(env, env->vtcm_log.va[i + j], \ - (dst >> (8 * j)) & 0xFF, ra); \ + (dst >> (8 * j)) & 0xFF, ra_); \ } \ } \ } \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 8ca3976a65..da10ac5847 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot) void HELPER(commit_hvx_stores)(CPUHexagonState *env) { uintptr_t ra = GETPC(); - int i; /* Normal (possibly masked) vector store */ - for (i = 0; i < VSTORES_MAX; i++) { + for (int i = 0; i < VSTORES_MAX; i++) { if (env->vstore_pending[i]) { env->vstore_pending[i] = 0; target_ulong va = env->vstore[i].va; @@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) g_assert_not_reached(); } } else { - for (i = 0; i < sizeof(MMVector); i++) { + for (int i = 0; i < sizeof(MMVector); i++) { if (test_bit(i, env->vtcm_log.mask)) { cpu_stb_data_ra(env, env->vtcm_log.va[i], env->vtcm_log.data.ub[i], ra); @@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args) static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx, uintptr_t retaddr) { - int i; - /* Normal (possibly masked) vector store */ - for (i = 0; i < VSTORES_MAX; i++) { + for (int i = 0; i < VSTORES_MAX; i++) { if (env->vstore_pending[i]) { target_ulong va = env->vstore[i].va; int size = env->vstore[i].size; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index c00254e4d5..ab708bf823 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -484,7 +484,6 @@ static void gen_start_packet(DisasContext *ctx) { Packet *pkt = ctx->pkt; target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; - int i; /* Clear out the disassembly context */ ctx->next_PC = next_PC; @@ -506,15 +505,15 @@ static void gen_start_packet(DisasContext *ctx) bitmap_zero(ctx->vregs_read, NUM_VREGS); bitmap_zero(ctx->qregs_read, NUM_QREGS); ctx->qreg_log_idx = 0; - for (i = 0; i < STORES_MAX; i++) { + for (int i = 0; i < STORES_MAX; i++) { ctx->store_width[i] = 0; } ctx->s1_store_processed = false; ctx->pre_commit = true; - for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { + for (int i = 0; i < TOTAL_PER_THREAD_REGS; i++) { ctx->new_value[i] = NULL; } - for (i = 0; i < NUM_PREGS; i++) { + for (int i = 0; i < NUM_PREGS; i++) { ctx->new_pred_value[i] = NULL; } @@ -1228,7 +1227,7 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, mem_log_stores[i].data64), store_val64_names[i]); } - for (int i = 0; i < VSTORES_MAX; i++) { + for (i = 0; i < VSTORES_MAX; i++) { snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); hex_vstore_addr[i] = tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, vstore[i].va),