From patchwork Thu Oct 5 22:22:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13410849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9B2FE92FC9 for ; Thu, 5 Oct 2023 22:23:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qoWk9-0005JT-9j; Thu, 05 Oct 2023 18:22:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qoWk4-0005Gx-A7 for qemu-devel@nongnu.org; Thu, 05 Oct 2023 18:22:49 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qoWjz-0008D8-L7 for qemu-devel@nongnu.org; Thu, 05 Oct 2023 18:22:47 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 395LlXsH031721; Thu, 5 Oct 2023 22:22:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=1OEQ/WoRAI1uE7ZIFOvj/Kuh//51BZK8kBZSyAmyseU=; b=mEgQKfN4mMEY4d4F//1JSVBf1K+56YE6av5/Me1nF+8zfekMrTLK+XH0WpGyAjKpQT23 2GRfSvJRKmwyYOiFdIqr9UfD+QnHPaVi+nbTYVPKB71xJlTBYW6kByvyy6SsR+gcg7F6 XjWCLULoet6RIA/EElkDnUmfCJljOI4/+zSdoIsztJAgLsMkV1ONajC2A3yOSaIwoxWC crzNZYYRxxDUkNOhnbpG0fNHqObaaayELMs+dFWzU3mcDo70bN/iT5aVBlL5mIwh5DkX M/CrK7PSn4NeKecwPv5QrqrHT6BQ/Xyvg18JWLIyuku2fqrWjLsI1dHr6zGuCk1ENVzL jw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3thfkh2ut5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Oct 2023 22:22:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 395MMVZ1015723 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 5 Oct 2023 22:22:31 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 5 Oct 2023 15:22:31 -0700 From: Brian Cain To: CC: , , , , , , , , , , Subject: [PATCH v2 3/3] target/hexagon: avoid shadowing globals Date: Thu, 5 Oct 2023 15:22:06 -0700 Message-ID: <20231005222206.2784853-4-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005222206.2784853-1-bcain@quicinc.com> References: <20231005222206.2784853-1-bcain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VYqt6bJgAppfSFwYcjMJm5Ny-SmD8_5r X-Proofpoint-ORIG-GUID: VYqt6bJgAppfSFwYcjMJm5Ny-SmD8_5r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_17,2023-10-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=585 malwarescore=0 phishscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050170 Received-SPF: pass client-ip=205.220.168.131; envelope-from=bcain@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the identifiers to avoid shadowing the type name. The global `cpu_env` is shadowed by local `cpu_env` arguments, so we rename the function arguments to avoid shadowing the global. Signed-off-by: Brian Cain Reviewed-by: Taylor Simpson --- target/hexagon/genptr.c | 56 ++++++++++++------------- target/hexagon/genptr.h | 18 ++++---- target/hexagon/mmvec/system_ext_mmvec.c | 4 +- target/hexagon/mmvec/system_ext_mmvec.h | 2 +- target/hexagon/op_helper.c | 4 +- 5 files changed, 42 insertions(+), 42 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 217bc7bb5a..11377ac92b 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) tcg_gen_deposit_i64(result, result, src64, N * 8, 8); } -static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) +static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int mem_index) { - tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL); - tcg_gen_mov_tl(hex_llsc_addr, vaddr); + tcg_gen_qemu_ld_tl(dest, v_addr, mem_index, MO_TEUL); + tcg_gen_mov_tl(hex_llsc_addr, v_addr); tcg_gen_mov_tl(hex_llsc_val, dest); } -static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index) +static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int mem_index) { - tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ); - tcg_gen_mov_tl(hex_llsc_addr, vaddr); + tcg_gen_qemu_ld_i64(dest, v_addr, mem_index, MO_TEUQ); + tcg_gen_mov_tl(hex_llsc_addr, v_addr); tcg_gen_mov_i64(hex_llsc_val_i64, dest); } static inline void gen_store_conditional4(DisasContext *ctx, - TCGv pred, TCGv vaddr, TCGv src) + TCGv pred, TCGv v_addr, TCGv src) { TCGLabel *fail = gen_new_label(); TCGLabel *done = gen_new_label(); TCGv one, zero, tmp; - tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); + tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail); one = tcg_constant_tl(0xff); zero = tcg_constant_tl(0); @@ -374,13 +374,13 @@ static inline void gen_store_conditional4(DisasContext *ctx, } static inline void gen_store_conditional8(DisasContext *ctx, - TCGv pred, TCGv vaddr, TCGv_i64 src) + TCGv pred, TCGv v_addr, TCGv_i64 src) { TCGLabel *fail = gen_new_label(); TCGLabel *done = gen_new_label(); TCGv_i64 one, zero, tmp; - tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); + tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail); one = tcg_constant_i64(0xff); zero = tcg_constant_i64(0); @@ -407,57 +407,57 @@ static TCGv gen_slotval(DisasContext *ctx) } #endif -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot) +void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot) { - tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_mov_tl(hex_store_addr[slot], v_addr); tcg_gen_movi_tl(hex_store_width[slot], width); tcg_gen_mov_tl(hex_store_val32[slot], src); } -void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot) { - gen_store32(vaddr, src, 1, slot); + gen_store32(v_addr, src, 1, slot); } -void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); - gen_store1(cpu_env, vaddr, tmp, slot); + gen_store1(cpu_env_, v_addr, tmp, slot); } -void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot) { - gen_store32(vaddr, src, 2, slot); + gen_store32(v_addr, src, 2, slot); } -void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); - gen_store2(cpu_env, vaddr, tmp, slot); + gen_store2(cpu_env_, v_addr, tmp, slot); } -void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot) { - gen_store32(vaddr, src, 4, slot); + gen_store32(v_addr, src, 4, slot); } -void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); - gen_store4(cpu_env, vaddr, tmp, slot); + gen_store4(cpu_env_, v_addr, tmp, slot); } -void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) +void gen_store8(TCGv_env cpu_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot) { - tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_mov_tl(hex_store_addr[slot], v_addr); tcg_gen_movi_tl(hex_store_width[slot], 8); tcg_gen_mov_i64(hex_store_val64[slot], src); } -void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot) +void gen_store8i(TCGv_env cpu_env_, TCGv v_addr, int64_t src, uint32_t slot) { TCGv_i64 tmp = tcg_constant_i64(src); - gen_store8(cpu_env, vaddr, tmp, slot); + gen_store8(cpu_env_, v_addr, tmp, slot); } TCGv gen_8bitsof(TCGv result, TCGv value) diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index a4b43c2910..b1289a3e78 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -24,15 +24,15 @@ extern const SemanticInsn opcode_genptr[]; -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot); -void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); -void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); -void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot); -void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot); -void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); -void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); -void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); -void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot); +void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot); +void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot); +void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot); +void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot); +void gen_store8(TCGv_env cpu_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot); +void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot); +void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot); +void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot); +void gen_store8i(TCGv_env cpu_env_, TCGv v_addr, int64_t src, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); TCGv get_result_gpr(DisasContext *ctx, int rnum); diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec/system_ext_mmvec.c index 8351f2cc01..c339eee38b 100644 --- a/target/hexagon/mmvec/system_ext_mmvec.c +++ b/target/hexagon/mmvec/system_ext_mmvec.c @@ -19,12 +19,12 @@ #include "cpu.h" #include "mmvec/system_ext_mmvec.h" -void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot) +void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot) { size_t size = sizeof(MMVector); env->vstore_pending[slot] = 1; - env->vstore[slot].va = vaddr; + env->vstore[slot].va = v_addr; env->vstore[slot].size = size; memcpy(&env->vstore[slot].data.ub[0], &env->tmp_VRegs[0], size); diff --git a/target/hexagon/mmvec/system_ext_mmvec.h b/target/hexagon/mmvec/system_ext_mmvec.h index bcefbffdf2..6a711fcb69 100644 --- a/target/hexagon/mmvec/system_ext_mmvec.h +++ b/target/hexagon/mmvec/system_ext_mmvec.h @@ -18,7 +18,7 @@ #ifndef HEXAGON_SYSTEM_EXT_MMVEC_H #define HEXAGON_SYSTEM_EXT_MMVEC_H -void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot); +void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot); void mem_vector_scatter_init(CPUHexagonState *env); void mem_vector_gather_init(CPUHexagonState *env); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index da10ac5847..aeafd78887 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -577,12 +577,12 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask) * wasn't cancelled), we have to do the store first. */ static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1, - uint32_t slot, target_ulong vaddr, int size, + uint32_t slot, target_ulong v_addr, int size, uintptr_t ra) { if (slot == 0 && pkt_has_store_s1 && ((env->slot_cancelled & (1 << 1)) == 0)) { - probe_read(env, vaddr, size, MMU_USER_IDX, ra); + probe_read(env, v_addr, size, MMU_USER_IDX, ra); commit_store(env, 1, ra); } }