@@ -515,6 +515,7 @@ M: Srivatsa Vaddagiri <quic_svaddagi@quicinc.com>
S: Maintained
F: accel/gunyah
F: include/sysemu/gunyah.h
+F: target/arm/arm_gicv3_gunyah.c
F: include/sysemu/gunyah_int.h
WHPX CPUs
@@ -410,3 +410,8 @@ static void gunyah_mem_ioeventfd_del(MemoryListener *listener,
exit(1);
}
}
+
+GUNYAHState *get_gunyah_state(void)
+{
+ return GUNYAH_STATE(current_accel());
+}
@@ -1937,6 +1937,8 @@ static void finalize_gic_version(VirtMachineState *vms)
gics_supported |= VIRT_GIC_VERSION_4_MASK;
}
}
+ } else if (gunyah_enabled()) {
+ gics_supported |= VIRT_GIC_VERSION_3_MASK;
} else {
error_report("Unsupported accelerator, can not determine GIC support");
exit(1);
@@ -32,6 +32,7 @@
#include "gicv3_internal.h"
#include "hw/arm/linux-boot-if.h"
#include "sysemu/kvm.h"
+#include "sysemu/gunyah.h"
static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
@@ -614,6 +615,8 @@ const char *gicv3_class_name(void)
{
if (kvm_irqchip_in_kernel()) {
return "kvm-arm-gicv3";
+ } else if (gunyah_enabled()) {
+ return "gunyah-arm-gicv3";
} else {
if (kvm_enabled()) {
error_report("Userspace GICv3 is not supported with KVM");
new file mode 100644
@@ -0,0 +1,106 @@
+/*
+ * QEMU Gunyah hypervisor support
+ *
+ * Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/intc/arm_gicv3_common.h"
+#include "qemu/error-report.h"
+#include "qemu/module.h"
+#include "sysemu/gunyah.h"
+#include "sysemu/gunyah_int.h"
+#include "sysemu/runstate.h"
+#include "gicv3_internal.h"
+#include "vgic_common.h"
+#include "migration/blocker.h"
+#include "qom/object.h"
+#include "target/arm/cpregs.h"
+#include "qemu/event_notifier.h"
+
+struct GUNYAHARMGICv3Class {
+ ARMGICv3CommonClass parent_class;
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
+#define TYPE_GUNYAH_ARM_GICV3 "gunyah-arm-gicv3"
+typedef struct GUNYAHARMGICv3Class GUNYAHARMGICv3Class;
+
+/* This is reusing the GICv3State typedef from ARM_GICV3_ITS_COMMON */
+DECLARE_OBJ_CHECKERS(GICv3State, GUNYAHARMGICv3Class,
+ GUNYAH_ARM_GICV3, TYPE_GUNYAH_ARM_GICV3)
+
+static EventNotifier *irq_notify;
+
+static void gunyah_arm_gicv3_set_irq(void *opaque, int irq, int level)
+{
+ GICv3State *s = (GICv3State *)opaque;
+
+ if (irq < s->num_irq - GIC_INTERNAL) {
+ event_notifier_set(&irq_notify[irq]);
+ }
+}
+
+static void gunyah_arm_gicv3_realize(DeviceState *dev, Error **errp)
+{
+ GICv3State *s = GUNYAH_ARM_GICV3(dev);
+ GUNYAHARMGICv3Class *ggc = GUNYAH_ARM_GICV3_GET_CLASS(s);
+ Error *local_err = NULL;
+ int i;
+ GUNYAHState *state = get_gunyah_state();
+
+ ggc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (s->revision != 3) {
+ error_setg(errp, "unsupported GIC revision %d for in-kernel GIC",
+ s->revision);
+ return;
+ }
+
+ gicv3_init_irqs_and_mmio(s, gunyah_arm_gicv3_set_irq, NULL);
+
+ irq_notify = g_malloc_n(s->num_irq - GIC_INTERNAL, sizeof(EventNotifier));
+
+ for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
+ event_notifier_init(&irq_notify[i], 0);
+ gunyah_add_irqfd(irq_notify[i].wfd, i, errp);
+ }
+
+ state->nr_irqs = s->num_irq - GIC_INTERNAL;
+}
+
+static void gunyah_arm_gicv3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ GUNYAHARMGICv3Class *ggc = GUNYAH_ARM_GICV3_CLASS(klass);
+
+ device_class_set_parent_realize(dc, gunyah_arm_gicv3_realize,
+ &ggc->parent_realize);
+ resettable_class_set_parent_phases(rc, NULL, NULL, NULL,
+ &ggc->parent_phases);
+}
+
+static const TypeInfo gunyah_arm_gicv3_info = {
+ .name = TYPE_GUNYAH_ARM_GICV3,
+ .parent = TYPE_ARM_GICV3_COMMON,
+ .instance_size = sizeof(GICv3State),
+ .class_init = gunyah_arm_gicv3_class_init,
+ .class_size = sizeof(GUNYAHARMGICv3Class),
+};
+
+static void gunyah_arm_gicv3_register_types(void)
+{
+ type_register_static(&gunyah_arm_gicv3_info);
+}
+
+type_init(gunyah_arm_gicv3_register_types)
@@ -25,6 +25,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/kvm.h"
+#include "sysemu/gunyah.h"
static int gicv3_its_pre_save(void *opaque)
{
@@ -165,6 +166,9 @@ const char *its_class_name(void)
if (kvm_irqchip_in_kernel()) {
/* KVM implementation requires this capability */
return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL;
+ } else if (gunyah_enabled()) {
+ /* ITS is not yet supported */
+ return NULL;
} else {
/* Software emulation based model */
return "arm-gicv3-its";
@@ -73,3 +73,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
+specific_ss.add(when: ['CONFIG_ARM_GIC', 'CONFIG_GUNYAH', 'TARGET_AARCH64'], if_true: files('arm_gicv3_gunyah.c'))
@@ -45,11 +45,13 @@ struct GUNYAHState {
bool is_protected_vm;
bool preshmem_reserved;
uint32_t preshmem_size;
+ uint32_t nr_irqs;
};
int gunyah_create_vm(void);
int gunyah_vm_ioctl(int type, ...);
void *gunyah_cpu_thread_fn(void *arg);
int gunyah_add_irqfd(int irqfd, int label, Error **errp);
+GUNYAHState *get_gunyah_state(void);
#endif /* GUNYAH_INT_H */
Gunyah hypervisor supports emulation of a GICv3 compatible interrupt controller. Emulation is handled by hypervisor itself, with Qemu being allowed to specify some of the properties such as IO address at which GICv3 should be mapped in guest address space. These properties are conveyed to hypervisor via the device-tree, which is parsed by hypervisor (or more specifically Resource Manager VM, which is the trusted agent of hypervisor), before VM begins execution. Injection of interrupts inside guest is supported by doorbell API of Gunyah hypervisor. Each doorbell is associated with a specific interrupt. An eventfd is created and associated with each doorbell/irq. Injection of a specific irq is accomplished by writing to the eventfd associated with that irq. Signed-off-by: Srivatsa Vaddagiri <quic_svaddagi@quicinc.com> --- MAINTAINERS | 1 + accel/gunyah/gunyah-all.c | 5 ++ hw/arm/virt.c | 2 + hw/intc/arm_gicv3_common.c | 3 + hw/intc/arm_gicv3_gunyah.c | 106 +++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 4 ++ hw/intc/meson.build | 1 + include/sysemu/gunyah_int.h | 2 + 8 files changed, 124 insertions(+) create mode 100644 hw/intc/arm_gicv3_gunyah.c