| Message ID | 20231110090557.3219206-2-jean-philippe@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/arm/virt: fix GIC maintenance IRQ registration | expand |
On Fri, 10 Nov 2023 at 09:07, Jean-Philippe Brucker <jean-philippe@linaro.org> wrote: > > Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"), > GIC maintenance IRQ registration fails on arm64: > > [ 0.979743] kvm [1]: Cannot register interrupt 9 > > That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case > where the maintenance IRQ is actually referred by its PPI index. Just > like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use > INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there > shouldn't be more similar issues. > > Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Isn't this already fixed by commit fa68ecb330dbd ? thanks -- PMM
On Fri, Nov 10, 2023 at 10:19:30AM +0000, Peter Maydell wrote: > On Fri, 10 Nov 2023 at 09:07, Jean-Philippe Brucker > <jean-philippe@linaro.org> wrote: > > > > Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"), > > GIC maintenance IRQ registration fails on arm64: > > > > [ 0.979743] kvm [1]: Cannot register interrupt 9 > > > > That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case > > where the maintenance IRQ is actually referred by its PPI index. Just > > like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use > > INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there > > shouldn't be more similar issues. > > > > Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > > Isn't this already fixed by commit fa68ecb330dbd ? No, that commit fixed the PMU interrupt (I copied most of its commit message and referenced it), but the GIC maintenance interrupt still needed to be fixed. Thanks, Jean
On Fri, 10 Nov 2023 at 11:45, Jean-Philippe Brucker <jean-philippe@linaro.org> wrote: > > On Fri, Nov 10, 2023 at 10:19:30AM +0000, Peter Maydell wrote: > > On Fri, 10 Nov 2023 at 09:07, Jean-Philippe Brucker > > <jean-philippe@linaro.org> wrote: > > > > > > Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"), > > > GIC maintenance IRQ registration fails on arm64: > > > > > > [ 0.979743] kvm [1]: Cannot register interrupt 9 > > > > > > That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case > > > where the maintenance IRQ is actually referred by its PPI index. Just > > > like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use > > > INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there > > > shouldn't be more similar issues. > > > > > > Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") > > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > > > > Isn't this already fixed by commit fa68ecb330dbd ? > > No, that commit fixed the PMU interrupt (I copied most of its commit > message and referenced it), but the GIC maintenance interrupt still needed > to be fixed. Ah, yes, I see now. Applied to target-arm.next, thanks. -- PMM
diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 783d71a1b3..f5e685b060 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -591,7 +591,8 @@ static void fdt_add_gic_node(VirtMachineState *vms) if (vms->virt) { qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } else { @@ -615,7 +616,8 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, vms->memmap[VIRT_GIC_VCPU].base, 2, vms->memmap[VIRT_GIC_VCPU].size); qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), GIC_FDT_IRQ_FLAGS_LEVEL_HI); } }
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic"), GIC maintenance IRQ registration fails on arm64: [ 0.979743] kvm [1]: Cannot register interrupt 9 That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case where the maintenance IRQ is actually referred by its PPI index. Just like commit fa68ecb330db ("hw/arm/virt: fix PMU IRQ registration"), use INITID_TO_PPI(). A search of "GIC_FDT_IRQ_TYPE_PPI" indicates that there shouldn't be more similar issues. Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> --- hw/arm/virt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)