| Message ID | 20231121071757.7178-2-ivan.klokov@syntacore.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix mmu translation with H extension | expand |
On 11/21/23 04:17, Ivan Klokov wrote: > According to RISCV privileged spec sect. 5.3.2 Virtual Address Translation Process > access-fault exceptions may raise only after PMA/PMP check. Current implementation > generates an access-fault for mbare mode even if there were no PMA/PMP errors. > This patch removes the erroneous MMU mode check and generates an access-fault > exception based on the pmp_violation flag only. > > Fixes: 1448689c7b ("target/riscv: Allow specifying MMU stage") > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu_helper.c | 30 +++++++----------------------- > 1 file changed, 7 insertions(+), 23 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b7af69de53..9ff0952e46 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1143,47 +1143,31 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, > bool two_stage_indirect) > { > CPUState *cs = env_cpu(env); > - int page_fault_exceptions, vm; > - uint64_t stap_mode; > - > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - stap_mode = SATP32_MODE; > - } else { > - stap_mode = SATP64_MODE; > - } > - > - if (first_stage) { > - vm = get_field(env->satp, stap_mode); > - } else { > - vm = get_field(env->hgatp, stap_mode); > - } > - > - page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; > > switch (access_type) { > case MMU_INST_FETCH: > if (env->virt_enabled && !first_stage) { > cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; > } else { > - cs->exception_index = page_fault_exceptions ? > - RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; > + cs->exception_index = pmp_violation ? > + RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; > } > break; > case MMU_DATA_LOAD: > if (two_stage && !first_stage) { > cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; > } else { > - cs->exception_index = page_fault_exceptions ? > - RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; > + cs->exception_index = pmp_violation ? > + RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; > } > break; > case MMU_DATA_STORE: > if (two_stage && !first_stage) { > cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; > } else { > - cs->exception_index = page_fault_exceptions ? > - RISCV_EXCP_STORE_PAGE_FAULT : > - RISCV_EXCP_STORE_AMO_ACCESS_FAULT; > + cs->exception_index = pmp_violation ? > + RISCV_EXCP_STORE_AMO_ACCESS_FAULT : > + RISCV_EXCP_STORE_PAGE_FAULT; > } > break; > default:
On Tue, Nov 21, 2023 at 6:51 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote: > > According to RISCV privileged spec sect. 5.3.2 Virtual Address Translation Process > access-fault exceptions may raise only after PMA/PMP check. Current implementation > generates an access-fault for mbare mode even if there were no PMA/PMP errors. > This patch removes the erroneous MMU mode check and generates an access-fault > exception based on the pmp_violation flag only. > > Fixes: 1448689c7b ("target/riscv: Allow specifying MMU stage") > > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Please keep existing tags when sending a new version if there aren't any changes Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 30 +++++++----------------------- > 1 file changed, 7 insertions(+), 23 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b7af69de53..9ff0952e46 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1143,47 +1143,31 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, > bool two_stage_indirect) > { > CPUState *cs = env_cpu(env); > - int page_fault_exceptions, vm; > - uint64_t stap_mode; > - > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - stap_mode = SATP32_MODE; > - } else { > - stap_mode = SATP64_MODE; > - } > - > - if (first_stage) { > - vm = get_field(env->satp, stap_mode); > - } else { > - vm = get_field(env->hgatp, stap_mode); > - } > - > - page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; > > switch (access_type) { > case MMU_INST_FETCH: > if (env->virt_enabled && !first_stage) { > cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; > } else { > - cs->exception_index = page_fault_exceptions ? > - RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; > + cs->exception_index = pmp_violation ? > + RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; > } > break; > case MMU_DATA_LOAD: > if (two_stage && !first_stage) { > cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; > } else { > - cs->exception_index = page_fault_exceptions ? > - RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; > + cs->exception_index = pmp_violation ? > + RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; > } > break; > case MMU_DATA_STORE: > if (two_stage && !first_stage) { > cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; > } else { > - cs->exception_index = page_fault_exceptions ? > - RISCV_EXCP_STORE_PAGE_FAULT : > - RISCV_EXCP_STORE_AMO_ACCESS_FAULT; > + cs->exception_index = pmp_violation ? > + RISCV_EXCP_STORE_AMO_ACCESS_FAULT : > + RISCV_EXCP_STORE_PAGE_FAULT; > } > break; > default: > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b7af69de53..9ff0952e46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1143,47 +1143,31 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, bool two_stage_indirect) { CPUState *cs = env_cpu(env); - int page_fault_exceptions, vm; - uint64_t stap_mode; - - if (riscv_cpu_mxl(env) == MXL_RV32) { - stap_mode = SATP32_MODE; - } else { - stap_mode = SATP64_MODE; - } - - if (first_stage) { - vm = get_field(env->satp, stap_mode); - } else { - vm = get_field(env->hgatp, stap_mode); - } - - page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; switch (access_type) { case MMU_INST_FETCH: if (env->virt_enabled && !first_stage) { cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { - cs->exception_index = page_fault_exceptions ? - RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; + cs->exception_index = pmp_violation ? + RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; } break; case MMU_DATA_LOAD: if (two_stage && !first_stage) { cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { - cs->exception_index = page_fault_exceptions ? - RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; + cs->exception_index = pmp_violation ? + RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; } break; case MMU_DATA_STORE: if (two_stage && !first_stage) { cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; } else { - cs->exception_index = page_fault_exceptions ? - RISCV_EXCP_STORE_PAGE_FAULT : - RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + cs->exception_index = pmp_violation ? + RISCV_EXCP_STORE_AMO_ACCESS_FAULT : + RISCV_EXCP_STORE_PAGE_FAULT; } break; default:
According to RISCV privileged spec sect. 5.3.2 Virtual Address Translation Process access-fault exceptions may raise only after PMA/PMP check. Current implementation generates an access-fault for mbare mode even if there were no PMA/PMP errors. This patch removes the erroneous MMU mode check and generates an access-fault exception based on the pmp_violation flag only. Fixes: 1448689c7b ("target/riscv: Allow specifying MMU stage") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> --- target/riscv/cpu_helper.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-)