@@ -10,9 +10,8 @@
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#endif
-#define RAM_SIZE 0x08000000 /* 128M */
-#define ROM_SIZE 0x00001000 /* 4k */
#define VECTORS_RESERVED_SIZE 0x1000
+#define STACK_SIZE 0x00100000
#if XCHAL_HAVE_BE
OUTPUT_FORMAT("elf32-xtensa-be")
@@ -21,18 +20,13 @@ OUTPUT_FORMAT("elf32-xtensa-le")
#endif
ENTRY(_start)
-MEMORY {
- ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = RAM_SIZE
- rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = ROM_SIZE
-}
-
SECTIONS
{
- .init :
+ .init XCHAL_RESET_VECTOR_VADDR :
{
*(.init)
*(.init.*)
- } > rom
+ }
#if XCHAL_HAVE_WINDOWED
.vector.window XCHAL_WINDOW_VECTORS_VADDR :
@@ -119,23 +113,16 @@ SECTIONS
*(.vector.kernel.*)
*(.vector.user.*)
*(.vector.double.*)
- } > ram
+ }
.text :
{
_ftext = .;
*(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
_etext = .;
- } > ram
+ }
- .rodata :
- {
- . = ALIGN(4);
- _frodata = .;
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- *(.rodata1)
- _erodata = .;
- } > ram
+ . = DATA_SEGMENT_ALIGN(0x1000, 0x1000);
.data :
{
@@ -146,7 +133,7 @@ SECTIONS
_gp = ALIGN(16);
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
- } > ram
+ }
.bss :
{
@@ -160,7 +147,8 @@ SECTIONS
*(COMMON)
_ebss = .;
_end = .;
- } > ram
-}
+ }
-PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16);
+ . = DATA_SEGMENT_END(.);
+ _fstack = ALIGN(. + STACK_SIZE, 16);
+}
Drop MEMORY clause and related size definitions and output section region specifications. Drop .rodata output section as the tests don't use it. Add DATA_SEGMENT_ALIGN/DATA_SEGMENT_END around .data and .bss to let the linker make an RW segment for data. Reserve 1M for stack instead of almost 128M. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> --- tests/tcg/xtensa/linker.ld.S | 34 +++++++++++----------------------- 1 file changed, 11 insertions(+), 23 deletions(-)