From patchwork Fri Jan 12 17:05:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?In=C3=A8s_Varhol?= X-Patchwork-Id: 13518639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84812C4706C for ; Fri, 12 Jan 2024 17:07:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rOKze-0005KE-Ap; Fri, 12 Jan 2024 12:06:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOKzc-0005IV-4U; Fri, 12 Jan 2024 12:06:52 -0500 Received: from zproxy2.enst.fr ([2001:660:330f:2::dd]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOKzY-000502-4G; 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Fri, 12 Jan 2024 18:06:41 +0100 (CET) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:240:fa97:9da:79c1:e167]) by zproxy2.enst.fr (Postfix) with ESMTPSA id 30A7A806B7; Fri, 12 Jan 2024 18:06:41 +0100 (CET) From: =?utf-8?q?In=C3=A8s_Varhol?= To: qemu-devel@nongnu.org Cc: Samuel Tardieu , Arnaud Minier , =?utf-8?q?In=C3=A8s_Varhol?= , Thomas Huth , Peter Maydell , qemu-arm@nongnu.org, Paolo Bonzini , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Laurent Vivier Subject: [RFC 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC Date: Fri, 12 Jan 2024 18:05:39 +0100 Message-ID: <20240112170635.303226-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112170635.303226-1-ines.varhol@telecom-paris.fr> References: <20240112170635.303226-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:660:330f:2::dd; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy2.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/Kconfig | 3 +- hw/arm/stm32l4x5_soc.c | 62 +++++++++++++++++++++++++++------- include/hw/arm/stm32l4x5_soc.h | 9 +++++ 3 files changed, 60 insertions(+), 14 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index bb4693bfbb..cb05147b64 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -459,8 +459,9 @@ config STM32L4X5_SOC bool select ARM_V7M select OR_IRQ - select STM32L4X5_SYSCFG select STM32L4X5_EXTI + select STM32L4X5_SYSCFG + select STM32L4X5_GPIO config XLNX_ZYNQMP_ARM bool diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 431f982caf..56a9a6affb 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -76,6 +76,17 @@ static const int exti_irq[NUM_EXTI_IRQ] = { 78 /* LCD wakeup, Direct */ }; +static const uint32_t gpio_addr[] = { + 0x48000000, + 0x48000400, + 0x48000800, + 0x48000C00, + 0x48001000, + 0x48001400, + 0x48001800, + 0x48001C00, +}; + static void stm32l4x5_soc_initfn(Object *obj) { Stm32l4x5SocState *s = STM32L4X5_SOC(obj); @@ -83,6 +94,15 @@ static void stm32l4x5_soc_initfn(Object *obj) object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI); object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG); + object_initialize_child(obj, "gpioa", &s->gpioa, TYPE_STM32L4X5_GPIO_A); + object_initialize_child(obj, "gpiob", &s->gpiob, TYPE_STM32L4X5_GPIO_B); + object_initialize_child(obj, "gpioc", &s->gpioc, TYPE_STM32L4X5_GPIO_C); + object_initialize_child(obj, "gpiod", &s->gpiod, TYPE_STM32L4X5_GPIO_D); + object_initialize_child(obj, "gpioe", &s->gpioe, TYPE_STM32L4X5_GPIO_E); + object_initialize_child(obj, "gpiof", &s->gpiof, TYPE_STM32L4X5_GPIO_F); + object_initialize_child(obj, "gpiog", &s->gpiog, TYPE_STM32L4X5_GPIO_G); + object_initialize_child(obj, "gpioh", &s->gpioh, TYPE_STM32L4X5_GPIO_H); + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } @@ -95,6 +115,7 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) MemoryRegion *system_memory = get_system_memory(); DeviceState *armv7m; SysBusDevice *busdev; + uint32_t pin_index; /* * We use s->refclk internally and only define it with qdev_init_clock_in() @@ -156,17 +177,40 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) return; } + /* GPIOs */ + const Stm32l4x5GpioState *gpios[] = { + &s->gpioa, + &s->gpiob, + &s->gpioc, + &s->gpiod, + &s->gpioe, + &s->gpiof, + &s->gpiog, + &s->gpioh, + }; + for (unsigned i = 0; i < NUM_GPIOS; i++) { + busdev = SYS_BUS_DEVICE(gpios[i]); + if (!sysbus_realize(busdev, errp)) { + return; + } + sysbus_mmio_map(busdev, 0, gpio_addr[i]); + } + /* System configuration controller */ busdev = SYS_BUS_DEVICE(&s->syscfg); if (!sysbus_realize(busdev, errp)) { return; } sysbus_mmio_map(busdev, 0, SYSCFG_ADDR); - /* - * TODO: when the GPIO device is implemented, connect it - * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and - * GPIO_NUM_PINS. - */ + + for (unsigned i = 0; i < NUM_GPIOS; i++) { + for (unsigned j = 0; j < GPIO_NUM_PINS; j++) { + pin_index = GPIO_NUM_PINS * i + j; + qdev_connect_gpio_out(DEVICE(gpios[i]), j, + qdev_get_gpio_in(DEVICE(&s->syscfg), + pin_index)); + } + } /* EXTI device */ busdev = SYS_BUS_DEVICE(&s->exti); @@ -256,14 +300,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) /* RESERVED: 0x40024400, 0x7FDBC00 */ /* AHB2 BUS */ - create_unimplemented_device("GPIOA", 0x48000000, 0x400); - create_unimplemented_device("GPIOB", 0x48000400, 0x400); - create_unimplemented_device("GPIOC", 0x48000800, 0x400); - create_unimplemented_device("GPIOD", 0x48000C00, 0x400); - create_unimplemented_device("GPIOE", 0x48001000, 0x400); - create_unimplemented_device("GPIOF", 0x48001400, 0x400); - create_unimplemented_device("GPIOG", 0x48001800, 0x400); - create_unimplemented_device("GPIOH", 0x48001C00, 0x400); /* RESERVED: 0x48002000, 0x7FDBC00 */ create_unimplemented_device("OTG_FS", 0x50000000, 0x40000); create_unimplemented_device("ADC", 0x50040000, 0x400); diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index baf70410b5..c8aff07b6d 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -28,6 +28,7 @@ #include "hw/arm/armv7m.h" #include "hw/misc/stm32l4x5_syscfg.h" #include "hw/misc/stm32l4x5_exti.h" +#include "hw/gpio/stm32l4x5_gpio.h" #include "qom/object.h" #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" @@ -43,6 +44,14 @@ struct Stm32l4x5SocState { Stm32l4x5ExtiState exti; Stm32l4x5SyscfgState syscfg; + Stm32l4x5GpioState gpioa; + Stm32l4x5GpioState gpiob; + Stm32l4x5GpioState gpioc; + Stm32l4x5GpioState gpiod; + Stm32l4x5GpioState gpioe; + Stm32l4x5GpioState gpiof; + Stm32l4x5GpioState gpiog; + Stm32l4x5GpioState gpioh; MemoryRegion sram1; MemoryRegion sram2;