From patchwork Mon Jan 22 06:34:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Cain X-Patchwork-Id: 13524852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85DA2C47DAF for ; Mon, 22 Jan 2024 06:36:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rRnuR-00037v-Jm; Mon, 22 Jan 2024 01:35:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rRnuC-0002xP-Rk for qemu-devel@nongnu.org; Mon, 22 Jan 2024 01:35:36 -0500 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rRnu7-0005il-A6 for qemu-devel@nongnu.org; Mon, 22 Jan 2024 01:35:36 -0500 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40M3QhM6010489; Mon, 22 Jan 2024 06:35:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s= qcppdkim1; bh=jB6KT4J6ii+XmNfDYPLYI1mkDqwUJqBk3/LdpjgPlDQ=; b=Qs gyxUXCmbzP2TycgZqVoQ0z5qh6YtwvLrU1flaJCqDgz1BF71C4tw4TUZ9NxXF8pX RSSLW1jd2z5RMZBXSkzmUlyGI2QMilKClNmMNkNvlaUYaDy7Zlt4/xKEapMGQwy2 aWpqNp2NEHLI8/VvmlyfLXn95YsyZRB7Gy1mOkc/q2XOa9gmQHG6qZttd2xG0cGF OVK6Wltfib9ikaTpuP9BRmT/BpQI/Q65fZils1H4SegBGuKlvSLqNxQ0BCtGCpSG Vmr6kvbaJC7moevOkWOVawOpj4KtVLmqH9dvzTFC/ijBn0Q68DGtKX5joL13A+xS Bbc91e6rpqbhf8pwNWOg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vr5gpk5fy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Jan 2024 06:35:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40M6ZS0m002706 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 Jan 2024 06:35:28 GMT Received: from hu-bcain-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 21 Jan 2024 22:35:27 -0800 From: Brian Cain To: CC: , , , , , , , , , , Subject: [PULL 09/15] Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs Date: Sun, 21 Jan 2024 22:34:55 -0800 Message-ID: <20240122063501.782041-10-bcain@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240122063501.782041-1-bcain@quicinc.com> References: <20240122063501.782041-1-bcain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Gl0F2-DkfRMKPHDk_6ke1k_rZHRxH_PS X-Proofpoint-ORIG-GUID: Gl0F2-DkfRMKPHDk_6ke1k_rZHRxH_PS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-21_04,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 mlxscore=0 malwarescore=0 impostorscore=0 mlxlogscore=859 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401220046 Received-SPF: pass client-ip=205.220.180.131; envelope-from=bcain@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Taylor Simpson This patch conflicts with https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html If that series goes in first, we'll rework this patch and vice versa. Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20231210220712.491494-8-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain --- target/hexagon/gen_analyze_funcs.py | 163 +--------------------------- target/hexagon/hex_common.py | 151 ++++++++++++++++++++++++++ 2 files changed, 157 insertions(+), 157 deletions(-) diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py index c3b521abef..a9af666cef 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -23,162 +23,6 @@ import hex_common -## -## Helpers for gen_analyze_func -## -def is_predicated(tag): - return "A_CONDEXEC" in hex_common.attribdict[tag] - - -def analyze_opn_old(f, tag, regtype, regid, regno): - regN = f"{regtype}{regid}N" - predicated = "true" if is_predicated(tag) else "false" - if regtype == "R": - if regid in {"ss", "tt"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n") - elif regid in {"dd", "ee", "xx", "yy"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n") - elif regid in {"s", "t", "u", "v"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - elif regid in {"d", "e", "x", "y"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "P": - if regid in {"s", "t", "u", "v"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_pred_read(ctx, {regN});\n") - elif regid in {"d", "e", "x"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_pred_write(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "C": - if regid == "ss": - f.write( - f" const int {regN} = insn->regno[{regno}] " - "+ HEX_REG_SA0;\n" - ) - f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n") - elif regid == "dd": - f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n") - f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n") - elif regid == "s": - f.write( - f" const int {regN} = insn->regno[{regno}] " - "+ HEX_REG_SA0;\n" - ) - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - elif regid == "d": - f.write(f" const int {regN} = insn->regno[{regno}] " "+ HEX_REG_SA0;\n") - f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "M": - if regid == "u": - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "V": - newv = "EXT_DFL" - if hex_common.is_new_result(tag): - newv = "EXT_NEW" - elif hex_common.is_tmp_result(tag): - newv = "EXT_TMP" - if regid in {"dd", "xx"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write( - f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{predicated});\n" - ) - elif regid in {"uu", "vv"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_read_pair(ctx, {regN});\n") - elif regid in {"s", "u", "v", "w"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_read(ctx, {regN});\n") - elif regid in {"d", "x", "y"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{predicated});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "Q": - if regid in {"d", "e", "x"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_qreg_write(ctx, {regN});\n") - elif regid in {"s", "t", "u", "v"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_qreg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "G": - if regid in {"dd"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - elif regid in {"d"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - elif regid in {"ss"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - elif regid in {"s"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "S": - if regid in {"dd"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - elif regid in {"d"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - elif regid in {"ss"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - elif regid in {"s"}: - f.write(f"// const int {regN} = insn->regno[{regno}];\n") - else: - hex_common.bad_register(regtype, regid) - else: - hex_common.bad_register(regtype, regid) - - -def analyze_opn_new(f, tag, regtype, regid, regno): - regN = f"{regtype}{regid}N" - if regtype == "N": - if regid in {"s", "t"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_reg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "P": - if regid in {"t", "u", "v"}: - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_pred_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - elif regtype == "O": - if regid == "s": - f.write(f" const int {regN} = insn->regno[{regno}];\n") - f.write(f" ctx_log_vreg_read(ctx, {regN});\n") - else: - hex_common.bad_register(regtype, regid) - else: - hex_common.bad_register(regtype, regid) - - -def analyze_opn(f, tag, regtype, regid, i): - if hex_common.is_pair(regid): - analyze_opn_old(f, tag, regtype, regid, i) - elif hex_common.is_single(regid): - if hex_common.is_old_val(regtype, regid, tag): - analyze_opn_old(f, tag, regtype, regid, i) - elif hex_common.is_new_val(regtype, regid, tag): - analyze_opn_new(f, tag, regtype, regid, i) - else: - hex_common.bad_register(regtype, regid) - else: - hex_common.bad_register(regtype, regid) - - ## ## Generate the code to analyze the instruction ## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;} @@ -203,7 +47,11 @@ def gen_analyze_func(f, tag, regs, imms): i = 0 ## Analyze all the registers for regtype, regid in regs: - analyze_opn(f, tag, regtype, regid, i) + reg = hex_common.get_register(tag, regtype, regid) + if reg.is_written(): + reg.analyze_write(f, tag, i) + else: + reg.analyze_read(f, i) i += 1 has_generated_helper = not hex_common.skip_qemu_helper( @@ -236,6 +84,7 @@ def main(): if is_idef_parser_enabled: hex_common.read_idef_parser_enabled_file(sys.argv[5]) hex_common.calculate_attribs() + hex_common.init_registers() tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index fc9ce4e2b0..4565dd1953 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -486,6 +486,12 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_reg_write(ctx, {self.reg_num}, {predicated}); + """)) class GprSource(Register, Single, OldSource): def decl_tcg(self, f, tag, regno): @@ -493,12 +499,22 @@ def decl_tcg(self, f, tag, regno): f.write(code_fmt(f"""\ TCGv {self.reg_tcg()} = hex_gpr[{self.reg_num}]; """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_reg_read(ctx, {self.reg_num}); + """)) class GprNewSource(Register, Single, NewSource): def decl_tcg(self, f, tag, regno): f.write(code_fmt(f"""\ TCGv {self.reg_tcg()} = get_result_gpr(ctx, insn->regno[{regno}]); """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_reg_read(ctx, {self.reg_num}); + """)) class GprReadWrite(Register, Single, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -517,6 +533,12 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_reg_write(ctx, {self.reg_num}, {predicated}); + """)) class ControlDest(Register, Single, Dest): def decl_reg_num(self, f, regno): @@ -532,6 +554,12 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_write_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_reg_write(ctx, {self.reg_num}, {predicated}); + """)) class ControlSource(Register, Single, OldSource): def decl_reg_num(self, f, regno): @@ -544,6 +572,11 @@ def decl_tcg(self, f, tag, regno): TCGv {self.reg_tcg()} = tcg_temp_new(); gen_read_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_reg_read(ctx, {self.reg_num}); + """)) class ModifierSource(Register, Single, OldSource): def decl_reg_num(self, f, regno): @@ -560,6 +593,11 @@ def decl_tcg(self, f, tag, regno): def idef_arg(self, declared): declared.append(self.reg_tcg()) declared.append("CS") + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_reg_read(ctx, {self.reg_num}); + """)) class PredDest(Register, Single, Dest): def decl_tcg(self, f, tag, regno): @@ -571,6 +609,11 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_pred_write(ctx, {self.reg_num}); + """)) class PredSource(Register, Single, OldSource): def decl_tcg(self, f, tag, regno): @@ -578,12 +621,22 @@ def decl_tcg(self, f, tag, regno): f.write(code_fmt(f"""\ TCGv {self.reg_tcg()} = hex_pred[{self.reg_num}]; """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_pred_read(ctx, {self.reg_num}); + """)) class PredNewSource(Register, Single, NewSource): def decl_tcg(self, f, tag, regno): f.write(code_fmt(f"""\ TCGv {self.reg_tcg()} = get_result_pred(ctx, insn->regno[{regno}]); """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_pred_read(ctx, {self.reg_num}); + """)) class PredReadWrite(Register, Single, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -596,6 +649,11 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_pred_write(ctx, {self.reg_num}); + """)) class PairDest(Register, Pair, Dest): def decl_tcg(self, f, tag, regno): @@ -608,6 +666,12 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated}); + """)) class PairSource(Register, Pair, OldSource): def decl_tcg(self, f, tag, regno): @@ -618,6 +682,11 @@ def decl_tcg(self, f, tag, regno): hex_gpr[{self.reg_num}], hex_gpr[{self.reg_num} + 1]); """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_reg_read_pair(ctx, {self.reg_num}); + """)) class PairReadWrite(Register, Pair, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -633,6 +702,12 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated}); + """)) class ControlPairDest(Register, Pair, Dest): def decl_reg_num(self, f, regno): @@ -649,6 +724,12 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_write_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated}); + """)) class ControlPairSource(Register, Pair, OldSource): def decl_reg_num(self, f, regno): @@ -661,6 +742,11 @@ def decl_tcg(self, f, tag, regno): TCGv_i64 {self.reg_tcg()} = tcg_temp_new_i64(); gen_read_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_reg_read_pair(ctx, {self.reg_num}); + """)) class VRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): @@ -680,6 +766,13 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + newv = hvx_newv(tag) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}); + """)) class VRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): @@ -696,6 +789,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */ """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_vreg_read(ctx, {self.reg_num}); + """)) class VRegNewSource(Register, Hvx, NewSource): def decl_tcg(self, f, tag, regno): @@ -709,6 +807,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */ """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_vreg_read(ctx, {self.reg_num}); + """)) class VRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -731,6 +834,13 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + newv = hvx_newv(tag) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}); + """)) class VRegTmp(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -755,6 +865,13 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + newv = hvx_newv(tag) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}); + """)) class VRegPairDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): @@ -774,6 +891,13 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + newv = hvx_newv(tag) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated}); + """)) class VRegPairSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): @@ -797,6 +921,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */ """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_vreg_read_pair(ctx, {self.reg_num}); + """)) class VRegPairReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -825,6 +954,13 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + newv = hvx_newv(tag) + predicated = "true" if is_predicated(tag) else "false" + f.write(code_fmt(f"""\ + ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicated}); + """)) class QRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): @@ -844,6 +980,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_qreg_write(ctx, {self.reg_num}); + """)) class QRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): @@ -861,6 +1002,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) + def analyze_read(self, f, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_qreg_read(ctx, {self.reg_num}); + """)) class QRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -883,6 +1029,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) + def analyze_write(self, f, tag, regno): + self.decl_reg_num(f, regno) + f.write(code_fmt(f"""\ + ctx_log_qreg_write(ctx, {self.reg_num}); + """)) def init_registers(): regs = {