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([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j18-20020a170902c3d200b001dbb06b6138sm889606plj.252.2024.02.16.05.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 05:57:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, max.chou@sifive.com, Daniel Henrique Barboza Subject: [PATCH v2 1/3] trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too Date: Fri, 16 Feb 2024 10:57:17 -0300 Message-ID: <20240216135719.1034289-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216135719.1034289-1-dbarboza@ventanamicro.com> References: <20240216135719.1034289-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the Vector spec section 3.2 [1]: "When mstatus.VS is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change mstatus.VS to Dirty." ldst_us_trans(), ldst_stride_trans(), ldst_index_trans() and ldst_whole_trans() will change vector state regardless of being a store op or not. Stores will set env->vstart to zero after execution (see vext_ldst_us() in vector_helper.c), and this is vector CSR state change. [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-start-index-csr-vstart Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context status") Signed-off-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9e101ab434..044c9c903e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -638,10 +638,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, fn(dest, mask, base, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -799,10 +796,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, fn(dest, mask, base, stride, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -906,10 +900,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, fn(dest, mask, base, index, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1104,9 +1095,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, fn(dest, base, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } + mark_vs_dirty(s); gen_set_label(over); return true;