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(dynamic-078-054-250-034.78.54.pool.telefonica.de. [78.54.250.34]) by smtp.gmail.com with ESMTPSA id b2-20020aa7c902000000b00564e489ce9asm906157edt.12.2024.03.09.05.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Mar 2024 05:41:10 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH 1/2] hw/pci-host/pam: Free PAMMemoryRegion from Intel-specific bit handling Date: Sat, 9 Mar 2024 14:40:55 +0100 Message-ID: <20240309134056.1605-2-shentey@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240309134056.1605-1-shentey@gmail.com> References: <20240309134056.1605-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=shentey@gmail.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The PAM bit extraction is currently spread across pam.c and the northbridge device models, making the extraction logic harder to comprehend. Also note how pam_update() deals with PAM_REGIONS_COUNT, even though it handles exactly one region. Fix this (at the cost of minor code duplication) by moving the bit extraction into the northbridge device models. As a side effect, pam_update() becomes less Intel-specific which would allow it to be reused e.g. in VIA northbridges. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/pam.h | 7 +++---- hw/pci-host/i440fx.c | 7 +++++-- hw/pci-host/pam.c | 14 +++++++------- hw/pci-host/q35.c | 5 +++-- 4 files changed, 18 insertions(+), 15 deletions(-) diff --git a/include/hw/pci-host/pam.h b/include/hw/pci-host/pam.h index 005916f826..b9b33aecc8 100644 --- a/include/hw/pci-host/pam.h +++ b/include/hw/pci-host/pam.h @@ -70,7 +70,6 @@ /* PAM registers: log nibble and high nibble*/ #define PAM_ATTR_WE ((uint8_t)2) #define PAM_ATTR_RE ((uint8_t)1) -#define PAM_ATTR_MASK ((uint8_t)3) /* SMRAM register */ #define SMRAM_D_OPEN ((uint8_t)(1 << 6)) @@ -83,13 +82,13 @@ #define PAM_REGIONS_COUNT 13 typedef struct PAMMemoryRegion { - MemoryRegion alias[4]; /* index = PAM value */ - unsigned current; + MemoryRegion alias[4]; /* index = mode value */ + uint8_t mode; } PAMMemoryRegion; void init_pam(PAMMemoryRegion *mem, Object *owner, MemoryRegion *ram, MemoryRegion *system, MemoryRegion *pci, uint32_t start, uint32_t size); -void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val); +void pam_update(PAMMemoryRegion *mem, uint8_t mode); #endif /* QEMU_PAM_H */ diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 4f0a0438d7..cddd506ab0 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -64,6 +64,8 @@ struct I440FXState { #define I440FX_PAM_SIZE 7 #define I440FX_SMRAM 0x72 +#define I440FX_PAM_ATTR_MASK ((uint8_t)3) + /* Keep it 2G to comply with older win32 guests */ #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) @@ -88,8 +90,9 @@ static void i440fx_update_memory_mappings(PCII440FXState *d) memory_region_transaction_begin(); for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { - pam_update(&d->pam_regions[i], i, - pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); + uint8_t reg = pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]; + pam_update(&d->pam_regions[i], + (reg >> ((!(i & 1)) * 4)) & I440FX_PAM_ATTR_MASK); } memory_region_set_enabled(&d->smram_region, !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); diff --git a/hw/pci-host/pam.c b/hw/pci-host/pam.c index 68e9884d27..29c0db097a 100644 --- a/hw/pci-host/pam.c +++ b/hw/pci-host/pam.c @@ -51,20 +51,20 @@ void init_pam(PAMMemoryRegion *mem, Object *owner, MemoryRegion *ram_memory, start, size); memory_region_transaction_begin(); - for (i = 0; i < 4; ++i) { + for (i = 0; i < ARRAY_SIZE(mem->alias); ++i) { memory_region_set_enabled(&mem->alias[i], false); memory_region_add_subregion_overlap(system_memory, start, &mem->alias[i], 1); } memory_region_transaction_commit(); - mem->current = 0; + mem->mode = 0; } -void pam_update(PAMMemoryRegion *pam, int idx, uint8_t val) +void pam_update(PAMMemoryRegion *pam, uint8_t mode) { - assert(0 <= idx && idx < PAM_REGIONS_COUNT); + g_assert(mode < ARRAY_SIZE(pam->alias)); - memory_region_set_enabled(&pam->alias[pam->current], false); - pam->current = (val >> ((!(idx & 1)) * 4)) & PAM_ATTR_MASK; - memory_region_set_enabled(&pam->alias[pam->current], true); + memory_region_set_enabled(&pam->alias[pam->mode], false); + pam->mode = mode; + memory_region_set_enabled(&pam->alias[pam->mode], true); } diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0d7d4e3f08..947d9aa9c4 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -330,8 +330,9 @@ static void mch_update_pam(MCHPCIState *mch) memory_region_transaction_begin(); for (i = 0; i < 13; i++) { - pam_update(&mch->pam_regions[i], i, - pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); + uint8_t reg = pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]; + pam_update(&mch->pam_regions[i], + (reg >> ((!(i & 1)) * 4)) & MCH_HOST_BRIDGE_PAM_MASK); } memory_region_transaction_commit(); }