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Thu, 21 Mar 2024 10:04:38 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7461958067; Thu, 21 Mar 2024 10:04:38 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:38 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 10/10] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Date: Thu, 21 Mar 2024 05:04:22 -0500 Message-Id: <20240321100422.5347-11-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fGjwtFZvLHRwOCdkRUO7BBULAIuKPu0g X-Proofpoint-ORIG-GUID: SVPjCPlUmgfaaLxJH9HAyzfaGA5WJtZg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a method to reset the value of LSI Source-ID. Mask off LSI source-id based on number of interrupts in the big/small PHB. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index f48750ee54..8fbaf6512e 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -489,6 +489,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); lsi_base <<= 3; + lsi_base &= (xsrc->nr_irqs - 1); /* TODO: handle reset values of PHB_LSI_SRC_ID */ if (!lsi_base) { @@ -1966,6 +1967,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb) /* TODO: Add more RO-masks as regs are implemented in the model */ } +static void pnv_phb4_fund_A_reset(PnvPHB4 *phb) +{ + phb->regs[PHB_LSI_SOURCE_ID >> 3] = PPC_BITMASK(4, 12); + pnv_phb4_update_xsrc(phb); +} + static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) { STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); @@ -2023,6 +2030,7 @@ static void pnv_phb4_reset(void *dev) pnv_phb4_cfg_core_reset(phb); pnv_phb4_pbl_core_reset(phb); + pnv_phb4_fund_A_reset(phb); pnv_phb4_err_reg_reset(phb); pnv_phb4_pcie_stack_reg_reset(phb); pnv_phb4_regb_err_reg_reset(phb); @@ -2102,8 +2110,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) return; } - pnv_phb4_update_xsrc(phb); - phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); pnv_phb4_xscom_realize(phb);