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Thu, 21 Mar 2024 10:04:34 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8E1C85805A; Thu, 21 Mar 2024 10:04:33 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:33 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 01/10] qtest/phb4: Add testbench for PHB4 Date: Thu, 21 Mar 2024 05:04:13 -0500 Message-Id: <20240321100422.5347-2-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: XlclDVvXX1rPE9gpz4Jkfqza7cB_ah4C X-Proofpoint-GUID: HRBOU0qF6-YPLCQZUKJ694SFpk-jnYqx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 mlxlogscore=795 spamscore=0 clxscore=1015 suspectscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org New qtest TB added for PHB4. TB reads PHB Version register and asserts that bits[24:31] have value 0xA5. Signed-off-by: Saif Abrar --- tests/qtest/meson.build | 1 + tests/qtest/pnv-phb4-test.c | 74 +++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 tests/qtest/pnv-phb4-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 36c5c13a7b..4795e51c17 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -168,6 +168,7 @@ qtests_ppc64 = \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : []) + \ + (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + \ (slirp.found() ? ['pxe-test'] : []) + \ (config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] : []) + \ diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c new file mode 100644 index 0000000000..e3b809e9c4 --- /dev/null +++ b/tests/qtest/pnv-phb4-test.c @@ -0,0 +1,74 @@ +/* + * QTest testcase for PowerNV PHB4 + * + * Copyright (c) 2024, IBM Corporation. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/pci-host/pnv_phb4_regs.h" + +#define P10_XSCOM_BASE 0x000603fc00000000ull +#define PHB4_MMIO 0x000600c3c0000000ull +#define PHB4_XSCOM 0x8010900ull + +#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) + +static uint64_t pnv_xscom_addr(uint32_t pcba) +{ + return P10_XSCOM_BASE | ((uint64_t) pcba << 3); +} + +static uint64_t pnv_phb4_xscom_addr(uint32_t reg) +{ + return pnv_xscom_addr(PHB4_XSCOM + reg); +} + +/* + * XSCOM read/write is indirect in PHB4: + * Write 'SCOM - HV Indirect Address Register' + * with register-offset to read/write. + - bit[0]: Valid Bit + - bit[51:61]: Indirect Address(00:10) + * Read/write 'SCOM - HV Indirect Data Register' to get/set the value. + */ + +static uint64_t pnv_phb4_xscom_read(QTestState *qts, uint32_t reg) +{ + qtest_writeq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_ADDR), + PPC_BIT(0) | reg); + return qtest_readq(qts, pnv_phb4_xscom_addr(PHB_SCOM_HV_IND_DATA)); +} + +/* Assert that 'PHB - Version Register Offset 0x0800' bits-[24:31] are 0xA5 */ +static void phb4_version_test(QTestState *qts) +{ + uint64_t ver = pnv_phb4_xscom_read(qts, PHB_VERSION); + + /* PHB Version register [24:31]: Major Revision ID 0xA5 */ + ver = ver >> (63 - 31); + g_assert_cmpuint(ver, ==, 0xA5); +} + +static void test_phb4(void) +{ + QTestState *qts = NULL; + + qts = qtest_initf("-machine powernv10 -accel tcg -nographic -d unimp"); + + /* Make sure test is running on PHB */ + phb4_version_test(qts); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("phb4", test_phb4); + return g_test_run(); +}