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Sun, 24 Mar 2024 09:09:53 +0100 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller , Sven Schnelle Subject: [PATCH 3/3] target/hppa: fix building gva for wide mode Date: Sun, 24 Mar 2024 09:09:45 +0100 Message-ID: <20240324080945.991100-4-svens@stackframe.org> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240324080945.991100-1-svens@stackframe.org> References: <20240324080945.991100-1-svens@stackframe.org> MIME-Version: 1.0 Received-SPF: pass client-ip=23.83.216.33; envelope-from=svens@stackframe.org; helo=chameleon.pear.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 64 Bit hppa no longer has a fixed 32/32 bit split between space and offset. Instead it uses 42 bits for the offset. The lower 10 bits of the space are always zero, leaving 22 bits actually used. Simply or the values together to build the gva. Signed-off-by: Sven Schnelle Reviewed-by: Helge Deller Tested-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/mem_helper.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 84785b5a5c..6f895fced7 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -523,13 +523,16 @@ void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg) } static void itlbt_pa20(CPUHPPAState *env, target_ulong r1, - target_ulong r2, vaddr va_b) + target_ulong r2, uint64_t spc, uint64_t off) { HPPATLBEntry *ent; - vaddr va_e; + vaddr va_b, va_e; uint64_t va_size; int mask_shift; + va_b = off & gva_offset_mask(env->psw); + va_b |= spc << 32; + mask_shift = 2 * (r1 & 0xf); va_size = (uint64_t)TARGET_PAGE_SIZE << mask_shift; va_b &= -va_size; @@ -569,14 +572,12 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong r1, void HELPER(idtlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) { - vaddr va_b = deposit64(env->cr[CR_IOR], 32, 32, env->cr[CR_ISR]); - itlbt_pa20(env, r1, r2, va_b); + itlbt_pa20(env, r1, r2, env->cr[CR_ISR], env->cr[CR_IOR]); } void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) { - vaddr va_b = deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]); - itlbt_pa20(env, r1, r2, va_b); + itlbt_pa20(env, r1, r2, env->cr[CR_IIASQ], env->cr[CR_IIAOQ]); } /* Purge (Insn/Data) TLB. */