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Tsirkin" CC: , Jason Wang , Huang Rui , Jiqian Chen Subject: [RFC QEMU PATCH v9 2/2] virtio-pci: implement No_Soft_Reset bit Date: Tue, 16 Apr 2024 15:01:27 +0800 Message-ID: <20240416070127.116922-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240416070127.116922-1-Jiqian.Chen@amd.com> References: <20240416070127.116922-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|IA0PR12MB8645:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e4b7c08-a869-4d01-3a6c-08dc5de3157f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aMqkSRPzBtZEUuRYZHFEdd37jz2dmPpIMLpEfPjUgDfceR/Rcd6QfU0uxgnGOBwimrRZzLock4ArWp8FfvQLpLhRpx6CVZ+2caLYLR0/N4aPW8bS0XUt2le3QwCtbgdJMRyt/cQbCUTk5MUXOqmC9x2kjIzXOllAiRuEqXml/xTLxujj/aqiyzu6aW7Awb0woCEXuIiXPfSHu+shbsBSZBiuU+SRLIbbNmPmw2oTlJJYA8uxo4TECOjztDb0oYHassqxJidgMJr2m8i63EE6wJFAYwtvwA4llInmrUdo5idUoo80zYA1mJrucmZyld53B6F9x6wBoROOn6IVpobWnGM5KP9SbQyl3U8IAOKU9Qszn4NW/Dvyu2Z2FtG7H06Dj/KOZjN+lshZbaDTrVbbsmYYeZok6rNw2b2f8rJWTP5BNs+sp/YIONBTiufP85heSdIhG9Nep9lu/q0KbDJEF5OIKHg5BBXGwS+lu389YGqDaW823NlZwSv5o7WTPUKA3zwPtJE2P5Ngwu+NEBTJ6PxvicPIyA1UffyBswaKO6wo2VxeUKSzn4zNrGcY9dUW2nizvZaAeEM/VoGDDADdEb97933hADUZRzFkBjJE0ygfLmpwQp92My/ogXVL1xsvBjSlZwFSs5tLTGLGWmu6MqE/QNZ1LmSK0A9r1RvbkwpG8Y7YW+uc4FrarhzkfFz5JLnjBUY2nAU5ysQWZWwz+JcNKrrM0euh95hYr7gDtFvSnqJEocQJwoS4ppxILKZ8 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(82310400014)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 07:01:47.8605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e4b7c08-a869-4d01-3a6c-08dc5de3157f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8645 Received-SPF: permerror client-ip=40.107.237.74; envelope-from=Jiqian.Chen@amd.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.185, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In current code, when guest does S3, virtio-gpu are reset due to the bit No_Soft_Reset is not set. After resetting, the display resources of virtio-gpu are destroyed, then the display can't come back and only show blank after resuming. Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check this bit, if this bit is set, the devices resetting will not be done, and then the display can work after resuming. No_Soft_Reset bit is implemented for all virtio devices, and was tested only on virtio-gpu device. Set it false by default for safety. Signed-off-by: Jiqian Chen --- hw/virtio/virtio-pci.c | 37 ++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-pci.h | 5 +++++ 2 files changed, 42 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a1b61308e7a0..82fa4defe5cd 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2230,6 +2230,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) pcie_cap_lnkctl_init(pci_dev); } + if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) { + pci_set_word(pci_dev->config + pos + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + } + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) { /* Init Power Management Control Register */ pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL, @@ -2292,11 +2297,37 @@ static void virtio_pci_reset(DeviceState *qdev) } } +static bool virtio_pci_no_soft_reset(PCIDevice *dev) +{ + uint16_t pmcsr; + + if (!pci_is_express(dev) || !dev->exp.pm_cap) { + return false; + } + + pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL); + + /* + * When No_Soft_Reset bit is set and the device + * is in D3hot state, don't reset device + */ + return (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3; +} + static void virtio_pci_bus_reset_hold(Object *obj) { PCIDevice *dev = PCI_DEVICE(obj); DeviceState *qdev = DEVICE(obj); + /* + * Note that: a proposal to add SUSPEND bit is being discussed, + * may need to consider the state of SUSPEND bit in future + */ + if (virtio_pci_no_soft_reset(dev)) { + return; + } + virtio_pci_reset(qdev); if (pci_is_express(dev)) { @@ -2336,6 +2367,12 @@ static Property virtio_pci_properties[] = { VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_PM_BIT, true), + /* + * for safety, set this false by default, if change it to true, + * need to consider compatible for old machine + */ + DEFINE_PROP_BIT("pcie-pm-no-soft-reset", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, false), DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_FLR_BIT, true), DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags, diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 59d88018c16a..9e67ba38c748 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -43,6 +43,7 @@ enum { VIRTIO_PCI_FLAG_INIT_FLR_BIT, VIRTIO_PCI_FLAG_AER_BIT, VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, }; /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -79,6 +80,10 @@ enum { /* Init Power Management */ #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT) +/* Init The No_Soft_Reset bit of Power Management */ +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \ + (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT) + /* Init Function Level Reset capability */ #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)