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Mon, 6 May 2024 11:31:55 -0400 (EDT) From: Jiaxun Yang Date: Mon, 06 May 2024 16:31:39 +0100 Subject: [PATCH 5/5] hw/mips/boston: Implement multi core support MIME-Version: 1.0 Message-Id: <20240506-mips-smp-v1-5-3cc234786910@flygoat.com> References: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com> In-Reply-To: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3546; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=agVUDK5z50Yx3y9FJ7dmchE1btUX/7dn7FnPDCPKZdk=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjSL74932Ov0zJsbZhlZfK82qc7fOjJkcyPHkS86fcG8u 14uOHuso5SFQYyDQVZMkSVEQKlvQ+PFBdcfZP2BmcPKBDKEgYtTACYSUs7IsM1m1rL8Kdnrwm0j urhjkv2cezff5zFSUyv/NmnF3A3rTjH80zUpFq3wsvK/79e70STjbpiDBkMs/51iEfa8oH3BCq3 8AA== X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass client-ip=64.147.123.150; envelope-from=jiaxun.yang@flygoat.com; helo=wfout7-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Implement multiple physical core support by passing topology to CPS subsystem and generate cpu-map fdt node to decribe new topology. Signed-off-by: Jiaxun Yang --- hw/mips/boston.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 1b44fb354c..4ed7d366fe 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -542,7 +542,10 @@ static const void *create_fdt(BostonState *s, qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); for (cpu = 0; cpu < ms->smp.cpus; cpu++) { + char *map_path; + name = g_strdup_printf("/cpus/cpu@%d", cpu); qemu_fdt_add_subnode(fdt, name); qemu_fdt_setprop_string(fdt, name, "compatible", "img,mips"); @@ -550,6 +553,27 @@ static const void *create_fdt(BostonState *s, qemu_fdt_setprop_cell(fdt, name, "reg", cpu); qemu_fdt_setprop_string(fdt, name, "device_type", "cpu"); qemu_fdt_setprop_cells(fdt, name, "clocks", clk_ph, FDT_BOSTON_CLK_CPU); + qemu_fdt_setprop_cell(fdt, name, "phandle", qemu_fdt_alloc_phandle(fdt)); + + if (ms->smp.threads > 1) { + map_path = g_strdup_printf( + "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", + cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), + (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, + (cpu / ms->smp.threads) % ms->smp.cores, + cpu % ms->smp.threads); + } else { + map_path = g_strdup_printf( + "/cpus/cpu-map/socket%d/cluster%d/core%d", + cpu / (ms->smp.clusters * ms->smp.cores), + (cpu / ms->smp.cores) % ms->smp.clusters, + cpu % ms->smp.cores); + } + + qemu_fdt_add_path(fdt, map_path); + qemu_fdt_setprop_phandle(fdt, map_path, "cpu", name); + + g_free(map_path); g_free(name); } @@ -591,6 +615,15 @@ static const void *create_fdt(BostonState *s, g_free(name); g_free(gic_name); + /* CM node */ + name = g_strdup_printf("/soc/cm@%" HWADDR_PRIx, memmap[BOSTON_CM].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "mti,mips-cm"); + qemu_fdt_setprop_cells(fdt, name, "reg", memmap[BOSTON_CM].base, + memmap[BOSTON_CM].size); + g_free(name); + + /* CDMM node */ name = g_strdup_printf("/soc/cdmm@%" HWADDR_PRIx, memmap[BOSTON_CDMM].base); qemu_fdt_add_subnode(fdt, name); @@ -703,7 +736,9 @@ static void boston_mach_init(MachineState *machine) object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, &error_fatal); - object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-pcore", machine->smp.cores, + &error_fatal); + object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.threads, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", qdev_get_clock_out(dev, "cpu-refclk"));