| Message ID | 20240520125157.311503-2-rkanwal@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Minor fixes and improvements for Virtual IRQs | expand |
On Mon, May 20, 2024 at 10:53 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote: > > AIA extends the width of all IRQ CSRs to 64bit even > in 32bit systems by adding missing half CSRs. > > This seems to be missed while adding support for > virtual IRQs. The whole logic seems to be correct > except the width of the masks. > > Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") > Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") > > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6b460ee0e8..152796ebc0 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1200,18 +1200,18 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | > */ > > /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */ > -static const target_ulong mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | > +static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | > LOCAL_INTERRUPTS; > -static const target_ulong mvien_writable_mask = MIP_SSIP | MIP_SEIP | > +static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP | > LOCAL_INTERRUPTS; > > -static const target_ulong sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; > -static const target_ulong hip_writable_mask = MIP_VSSIP; > -static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > +static const uint64_t sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; > +static const uint64_t hip_writable_mask = MIP_VSSIP; > +static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > MIP_VSEIP | LOCAL_INTERRUPTS; > -static const target_ulong hvien_writable_mask = LOCAL_INTERRUPTS; > +static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS; > > -static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; > +static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; > > const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > -- > 2.34.1 > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b460ee0e8..152796ebc0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1200,18 +1200,18 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | */ /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */ -static const target_ulong mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | +static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | LOCAL_INTERRUPTS; -static const target_ulong mvien_writable_mask = MIP_SSIP | MIP_SEIP | +static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP | LOCAL_INTERRUPTS; -static const target_ulong sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; -static const target_ulong hip_writable_mask = MIP_VSSIP; -static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | +static const uint64_t sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; +static const uint64_t hip_writable_mask = MIP_VSSIP; +static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | LOCAL_INTERRUPTS; -static const target_ulong hvien_writable_mask = LOCAL_INTERRUPTS; +static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS; -static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; +static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true,
AIA extends the width of all IRQ CSRs to 64bit even in 32bit systems by adding missing half CSRs. This seems to be missed while adding support for virtual IRQs. The whole logic seems to be correct except the width of the masks. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/csr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)