diff mbox series

[2/2] target/loongarch: Add loongson binary translation feature

Message ID 20240521080549.434197-3-maobibo@loongson.cn (mailing list archive)
State New, archived
Headers show
Series target/loongarch: Add loongson binary translation feature | expand

Commit Message

Bibo Mao May 21, 2024, 8:05 a.m. UTC 
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).

Now LBT feature is added in kvm mode, not supported in TCG mode since
it is not emulated. And only LBT feature is added here, LBT register
saving and restoring is not supported since it depeeds on LBT feautre
implemented in KVM kernel.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c                | 32 +++++++++++++++++++++++++++
 target/loongarch/cpu.h                |  1 +
 target/loongarch/loongarch-qmp-cmds.c |  2 +-
 3 files changed, 34 insertions(+), 1 deletion(-)

Comments

gaosong May 22, 2024, 8:24 a.m. UTC | #1 
在 2024/5/21 下午4:05, Bibo Mao 写道:
> Loongson Binary Translation (LBT) is used to accelerate binary
> translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
> eflags (eflags) and x87 fpu stack pointer (ftop).
>
> Now LBT feature is added in kvm mode, not supported in TCG mode since
> it is not emulated. And only LBT feature is added here, LBT register
> saving and restoring is not supported since it depeeds on LBT feautre
> implemented in KVM kernel.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao
>   target/loongarch/cpu.c                | 32 +++++++++++++++++++++++++++
>   target/loongarch/cpu.h                |  1 +
>   target/loongarch/loongarch-qmp-cmds.c |  2 +-
>   3 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index b5c1ec94af..84254c0f42 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -412,6 +412,9 @@ static void loongarch_la464_initfn(Object *obj)
>       data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
>       data = FIELD_DP32(data, CPUCFG2, LSPW, 1);
>       data = FIELD_DP32(data, CPUCFG2, LAM, 1);
> +    if (kvm_enabled()) {
> +        data = FIELD_DP32(data, CPUCFG2, LBT_ALL, 7);
> +    }
>       env->cpucfg[2] = data;
>   
>       env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
> @@ -643,12 +646,41 @@ static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
>       }
>   }
>   
> +static bool loongarch_get_lbt(Object *obj, Error **errp)
> + {
> +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> +    bool ret;
> +
> +    ret = false;
> +    /* lbt is enabled only in kvm mode, not supported in tcg mode */
> +    if (kvm_enabled() &&
> +        (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL) == 7)) {
> +        ret = true;
> +     }
> +    return ret;
> +}
> +
> +static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
> +{
> +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> +    int lbt;
> +
> +    lbt = 0;
> +    if (kvm_enabled() && value) {
> +        /* Enable binary translation for all architectures */
> +        lbt = 7;
> +    }
> +    cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL, lbt);
> +}
> +
>   void loongarch_cpu_post_init(Object *obj)
>   {
>       object_property_add_bool(obj, "lsx", loongarch_get_lsx,
>                                loongarch_set_lsx);
>       object_property_add_bool(obj, "lasx", loongarch_get_lasx,
>                                loongarch_set_lasx);
> +    object_property_add_bool(obj, "lbt", loongarch_get_lbt,
> +                             loongarch_set_lbt);
>   }
>   
>   static void loongarch_cpu_init(Object *obj)
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 41b8e6d96d..2021e85303 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -152,6 +152,7 @@ FIELD(CPUCFG2, LLFTP_VER, 15, 3)
>   FIELD(CPUCFG2, LBT_X86, 18, 1)
>   FIELD(CPUCFG2, LBT_ARM, 19, 1)
>   FIELD(CPUCFG2, LBT_MIPS, 20, 1)
> +FIELD(CPUCFG2, LBT_ALL, 18, 3)
>   FIELD(CPUCFG2, LSPW, 21, 1)
>   FIELD(CPUCFG2, LAM, 22, 1)
>   
> diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
> index 8721a5eb13..c6f6e1ef85 100644
> --- a/target/loongarch/loongarch-qmp-cmds.c
> +++ b/target/loongarch/loongarch-qmp-cmds.c
> @@ -40,7 +40,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
>   }
>   
>   static const char *cpu_model_advertised_features[] = {
> -    "lsx", "lasx", NULL
> +    "lsx", "lasx", "lbt", NULL
>   };
>   
>   CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
diff mbox series

Patch

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b5c1ec94af..84254c0f42 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -412,6 +412,9 @@  static void loongarch_la464_initfn(Object *obj)
     data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
     data = FIELD_DP32(data, CPUCFG2, LSPW, 1);
     data = FIELD_DP32(data, CPUCFG2, LAM, 1);
+    if (kvm_enabled()) {
+        data = FIELD_DP32(data, CPUCFG2, LBT_ALL, 7);
+    }
     env->cpucfg[2] = data;
 
     env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
@@ -643,12 +646,41 @@  static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
     }
 }
 
+static bool loongarch_get_lbt(Object *obj, Error **errp)
+ {
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    bool ret;
+
+    ret = false;
+    /* lbt is enabled only in kvm mode, not supported in tcg mode */
+    if (kvm_enabled() &&
+        (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL) == 7)) {
+        ret = true;
+     }
+    return ret;
+}
+
+static void loongarch_set_lbt(Object *obj, bool value, Error **errp)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    int lbt;
+
+    lbt = 0;
+    if (kvm_enabled() && value) {
+        /* Enable binary translation for all architectures */
+        lbt = 7;
+    }
+    cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LBT_ALL, lbt);
+}
+
 void loongarch_cpu_post_init(Object *obj)
 {
     object_property_add_bool(obj, "lsx", loongarch_get_lsx,
                              loongarch_set_lsx);
     object_property_add_bool(obj, "lasx", loongarch_get_lasx,
                              loongarch_set_lasx);
+    object_property_add_bool(obj, "lbt", loongarch_get_lbt,
+                             loongarch_set_lbt);
 }
 
 static void loongarch_cpu_init(Object *obj)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 41b8e6d96d..2021e85303 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -152,6 +152,7 @@  FIELD(CPUCFG2, LLFTP_VER, 15, 3)
 FIELD(CPUCFG2, LBT_X86, 18, 1)
 FIELD(CPUCFG2, LBT_ARM, 19, 1)
 FIELD(CPUCFG2, LBT_MIPS, 20, 1)
+FIELD(CPUCFG2, LBT_ALL, 18, 3)
 FIELD(CPUCFG2, LSPW, 21, 1)
 FIELD(CPUCFG2, LAM, 22, 1)
 
diff --git a/target/loongarch/loongarch-qmp-cmds.c b/target/loongarch/loongarch-qmp-cmds.c
index 8721a5eb13..c6f6e1ef85 100644
--- a/target/loongarch/loongarch-qmp-cmds.c
+++ b/target/loongarch/loongarch-qmp-cmds.c
@@ -40,7 +40,7 @@  CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 }
 
 static const char *cpu_model_advertised_features[] = {
-    "lsx", "lasx", NULL
+    "lsx", "lasx", "lbt", NULL
 };
 
 CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,