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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fcfe648bsm3457182b3a.168.2024.05.26.05.26.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 05:26:43 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Caleb Schlossin , =?utf-8?q?C=C3=A9dric_Le_Goate?= =?utf-8?q?r?= , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Date: Sun, 26 May 2024 22:26:07 +1000 Message-ID: <20240526122612.473476-7-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240526122612.473476-1-npiggin@gmail.com> References: <20240526122612.473476-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The way SMT thread siblings are matched is clunky, using hard-coded logic that checks the PIR SPR. Change that to use a new core_index variable in the CPUPPCState, where all siblings have the same core_index. CPU realize routines have flexibility in setting core/sibling topology. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 5 ++++- hw/ppc/pnv_core.c | 2 ++ hw/ppc/spapr_cpu_core.c | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index dac13d4dac..9a89083932 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1247,6 +1247,9 @@ struct CPUArchState { /* when a memory exception occurs, the access type is stored here */ int access_type; + /* For SMT processors */ + int core_index; + #if !defined(CONFIG_USER_ONLY) /* MMU context, only relevant for full system emulation */ #if defined(TARGET_PPC64) @@ -1404,7 +1407,7 @@ struct CPUArchState { }; #define _CORE_ID(cs) \ - (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1)) + (POWERPC_CPU(cs)->env.core_index) #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ CPU_FOREACH(cs_sibling) \ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 9b5edd9e48..0f61aabb77 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -252,6 +252,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, pir_spr->default_value = pir; tir_spr->default_value = tir; + env->core_index = core_hwid; + /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index e7c9edd033..059d372c8a 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -300,16 +300,19 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) g_autofree char *id = NULL; CPUState *cs; PowerPCCPU *cpu; + CPUPPCState *env; obj = object_new(scc->cpu_type); cs = CPU(obj); cpu = POWERPC_CPU(obj); + env = &cpu->env; /* * All CPUs start halted. CPU0 is unhalted from the machine level reset code * and the rest are explicitly started up by the guest using an RTAS call. */ qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true); + env->core_index = cc->core_id; cs->cpu_index = cc->core_id + i; if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) { return NULL;