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Mon, 3 Jun 2024 05:59:55 +0000 From: CLEMENT MATHIEU--DRIF To: "qemu-devel@nongnu.org" CC: "jasowang@redhat.com" , "zhenzhong.duan@intel.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "joao.m.martins@oracle.com" , "peterx@redhat.com" , "mst@redhat.com" , CLEMENT MATHIEU--DRIF Subject: [PATCH ats_vtd v5 22/22] intel_iommu: add support for ATS Thread-Topic: [PATCH ats_vtd v5 22/22] intel_iommu: add support for ATS Thread-Index: AQHatXtByK+MPvyRxk6nyjnkNV88Ag== Date: Mon, 3 Jun 2024 05:59:55 +0000 Message-ID: <20240603055917.18735-23-clement.mathieu--drif@eviden.com> References: <20240603055917.18735-1-clement.mathieu--drif@eviden.com> In-Reply-To: <20240603055917.18735-1-clement.mathieu--drif@eviden.com> Accept-Language: en-GB, fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=eviden.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: AM8PR07MB7602:EE_|AM8PR07MB8192:EE_ x-ms-office365-filtering-correlation-id: eda0d791-07dc-4726-05fd-08dc83926469 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 ++++++++++++++++++++++++++++++++-- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1ba43f59b5..d12441430f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5381,12 +5381,10 @@ static void vtd_report_ir_illegal_access(VTDAddressSpace *vtd_as, bool is_fpd_set = false; VTDContextEntry ce; - assert(vtd_as->pasid != PCI_NO_PASID); - /* Try out best to fetch FPD, we can't do anything more */ if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) { is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; - if (!is_fpd_set && s->root_scalable) { + if (!is_fpd_set && s->root_scalable && vtd_as->pasid != PCI_NO_PASID) { vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid); } } @@ -6004,6 +6002,75 @@ static IOMMUMemoryRegion *vtd_get_memory_region_pasid(PCIBus *bus, return &vtd_as->iommu; } +static IOMMUTLBEntry vtd_iommu_ats_do_translate(IOMMUMemoryRegion *iommu, + hwaddr addr, + IOMMUAccessFlags flags, + int iommu_idx) +{ + IOMMUTLBEntry entry; + VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); + + if (vtd_is_interrupt_addr(addr)) { + vtd_report_ir_illegal_access(vtd_as, addr, flags & IOMMU_WO); + entry.iova = 0; + entry.translated_addr = 0; + entry.addr_mask = ~VTD_PAGE_MASK_4K; + entry.perm = IOMMU_NONE; + entry.pasid = PCI_NO_PASID; + } else { + entry = vtd_iommu_translate(iommu, addr, flags, iommu_idx); + } + return entry; +} + +static ssize_t vtd_iommu_ats_request_translation(IOMMUMemoryRegion *iommu, + bool priv_req, bool exec_req, + hwaddr addr, size_t length, + bool no_write, + IOMMUTLBEntry *result, + size_t result_length, + uint32_t *err_count) +{ + IOMMUAccessFlags flags = IOMMU_ACCESS_FLAG_FULL(true, !no_write, exec_req, + priv_req, false, false); + ssize_t res_index = 0; + hwaddr target_address = addr + length; + IOMMUTLBEntry entry; + + *err_count = 0; + + while ((addr < target_address) && (res_index < result_length)) { + entry = vtd_iommu_ats_do_translate(iommu, addr, flags, 0); + if (!IOMMU_TLB_ENTRY_TRANSLATION_ERROR(&entry)) { /* Translation done */ + if (no_write) { + /* The device should not use this entry for a write access */ + entry.perm &= ~IOMMU_WO; + } + /* + * 4.1.2 : Global Mapping (G) : Remapping hardware provides a value + * of 0 in this field + */ + entry.perm &= ~IOMMU_GLOBAL; + } else { + *err_count += 1; + } + result[res_index] = entry; + res_index += 1; + addr = (addr & (~entry.addr_mask)) + (entry.addr_mask + 1); + } + + /* Buffer too small */ + if (addr < target_address) { + return -ENOMEM; + } + return res_index; +} + +static uint64_t vtd_get_min_page_size(IOMMUMemoryRegion *iommu) +{ + return VTD_PAGE_SIZE; +} + static PCIIOMMUOps vtd_iommu_ops = { .get_address_space = vtd_host_dma_iommu, .get_address_space_pasid = vtd_host_dma_iommu_pasid, @@ -6210,6 +6277,8 @@ static void vtd_iommu_memory_region_class_init(ObjectClass *klass, imrc->translate = vtd_iommu_translate; imrc->notify_flag_changed = vtd_iommu_notify_flag_changed; imrc->replay = vtd_iommu_replay; + imrc->iommu_ats_request_translation = vtd_iommu_ats_request_translation; + imrc->get_min_page_size = vtd_get_min_page_size; } static const TypeInfo vtd_iommu_memory_region_info = { diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 1b0d8958ad..461158f588 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -194,6 +194,7 @@ #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_NEST (1ULL << 26) #define VTD_ECAP_SRS (1ULL << 31) +#define VTD_ECAP_NWFS (1ULL << 33) #define VTD_ECAP_PSS (19ULL << 35) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43)