| Message ID | 20240617185804.25075-24-itachis@FreeBSD.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM AArch64 Support for BSD | expand |
On 6/17/24 11:58, Ajeet Singh wrote: > From: Stacey Son <sson@FreeBSD.org> > > Function checks the processor state to ensure that the current > execution mode is EL0 and no flags indicating interrupts or > exceptions are set > > Signed-off-by: Stacey Son <sson@FreeBSD.org> > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> > --- > bsd-user/aarch64/signal.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c > index 13faac8ce6..ad81531ec5 100644 > --- a/bsd-user/aarch64/signal.c > +++ b/bsd-user/aarch64/signal.c > @@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag) > > return err; > } > + > +/* Compare to sys_sigreturn() in arm64/arm64/machdep.c */ > +abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf, > + abi_ulong *target_uc) > +{ > + uint32_t pstate = pstate_read(regs); > + > + *target_uc = 0; > + > + if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t || > + (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) { > + return -TARGET_EINVAL; > + } > + > + *target_uc = target_sf; Why delay this store? I don't see why you're assigning 0 above. r~
On Tue, Jun 18, 2024 at 4:56 PM Richard Henderson < richard.henderson@linaro.org> wrote: > On 6/17/24 11:58, Ajeet Singh wrote: > > From: Stacey Son <sson@FreeBSD.org> > > > > Function checks the processor state to ensure that the current > > execution mode is EL0 and no flags indicating interrupts or > > exceptions are set > > > > Signed-off-by: Stacey Son <sson@FreeBSD.org> > > Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> > > --- > > bsd-user/aarch64/signal.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c > > index 13faac8ce6..ad81531ec5 100644 > > --- a/bsd-user/aarch64/signal.c > > +++ b/bsd-user/aarch64/signal.c > > @@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, > target_mcontext_t *mcp, int srflag) > > > > return err; > > } > > + > > +/* Compare to sys_sigreturn() in arm64/arm64/machdep.c */ > This is now in exec_machdep.c and the most relevant bits are set_mcontext() and sys_sigreturn(). > > +abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf, > > + abi_ulong *target_uc) > > +{ > > + uint32_t pstate = pstate_read(regs); > > + > > + *target_uc = 0; > > + > > + if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t || > > + (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) { > > + return -TARGET_EINVAL; > > + } > > + > > + *target_uc = target_sf; > > Why delay this store? I don't see why you're assigning 0 above. > I'm not sure I understand this either.... We don't store anything when there's an error in the pstate, at least in the kernel code. Warner
diff --git a/bsd-user/aarch64/signal.c b/bsd-user/aarch64/signal.c index 13faac8ce6..ad81531ec5 100644 --- a/bsd-user/aarch64/signal.c +++ b/bsd-user/aarch64/signal.c @@ -117,3 +117,21 @@ abi_long set_mcontext(CPUARMState *regs, target_mcontext_t *mcp, int srflag) return err; } + +/* Compare to sys_sigreturn() in arm64/arm64/machdep.c */ +abi_long get_ucontext_sigreturn(CPUARMState *regs, abi_ulong target_sf, + abi_ulong *target_uc) +{ + uint32_t pstate = pstate_read(regs); + + *target_uc = 0; + + if ((pstate & PSTATE_M) != PSTATE_MODE_EL0t || + (pstate & (PSTATE_F | PSTATE_I | PSTATE_A | PSTATE_D)) != 0) { + return -TARGET_EINVAL; + } + + *target_uc = target_sf; + + return 0; +}