diff mbox series

[v4,3/3] tests/qtest: Check STM32L4x5 clock connections

Message ID 20240622094402.244604-4-ines.varhol@telecom-paris.fr (mailing list archive)
State New, archived
Headers show
Series Check clock connection between STM32L4x5 RCC and peripherals | expand

Commit Message

Inès Varhol June 22, 2024, 9:43 a.m. UTC 
For USART, GPIO and SYSCFG devices, check that clock frequency before
and after enabling the peripheral clock in RCC is correct.

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/stm32l4x5.h             | 42 +++++++++++++++++++++++++++++
 tests/qtest/stm32l4x5_gpio-test.c   | 23 ++++++++++++++++
 tests/qtest/stm32l4x5_syscfg-test.c | 20 ++++++++++++--
 tests/qtest/stm32l4x5_usart-test.c  | 26 ++++++++++++++++++
 4 files changed, 109 insertions(+), 2 deletions(-)
 create mode 100644 tests/qtest/stm32l4x5.h

Comments

Luc Michel July 1, 2024, 6:43 p.m. UTC | #1 
On 11:43 Sat 22 Jun     , Inès Varhol wrote:
> For USART, GPIO and SYSCFG devices, check that clock frequency before
> and after enabling the peripheral clock in RCC is correct.
> 
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Luc Michel <luc@lmichel.fr>

> ---
>  tests/qtest/stm32l4x5.h             | 42 +++++++++++++++++++++++++++++
>  tests/qtest/stm32l4x5_gpio-test.c   | 23 ++++++++++++++++
>  tests/qtest/stm32l4x5_syscfg-test.c | 20 ++++++++++++--
>  tests/qtest/stm32l4x5_usart-test.c  | 26 ++++++++++++++++++
>  4 files changed, 109 insertions(+), 2 deletions(-)
>  create mode 100644 tests/qtest/stm32l4x5.h
> 
> diff --git a/tests/qtest/stm32l4x5.h b/tests/qtest/stm32l4x5.h
> new file mode 100644
> index 0000000000..2d21cc666c
> --- /dev/null
> +++ b/tests/qtest/stm32l4x5.h
> @@ -0,0 +1,42 @@
> +/*
> + * QTest testcase header for STM32L4X5 :
> + * used for consolidating common objects in stm32l4x5_*-test.c
> + *
> + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
> + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "libqtest.h"
> +
> +/* copied from clock.h */
> +#define CLOCK_PERIOD_1SEC (1000000000llu << 32)
> +#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_PERIOD_1SEC / (hz) : 0u)
> +/*
> + * MSI (4 MHz) is used as system clock source after startup
> + * from Reset.
> + * AHB, APB1 and APB2 prescalers are set to 1 at reset.
> + */
> +#define SYSCLK_PERIOD CLOCK_PERIOD_FROM_HZ(4000000)
> +#define RCC_AHB2ENR 0x4002104C
> +#define RCC_APB1ENR1 0x40021058
> +#define RCC_APB1ENR2 0x4002105C
> +#define RCC_APB2ENR 0x40021060
> +
> +
> +static inline uint64_t get_clock_period(QTestState *qts, const char *path)
> +{
> +    uint64_t clock_period = 0;
> +    QDict *r;
> +
> +    r = qtest_qmp(qts, "{ 'execute': 'qom-get', 'arguments':"
> +        " { 'path': %s, 'property': 'qtest-clock-period'} }", path);
> +    g_assert_false(qdict_haskey(r, "error"));
> +    clock_period = qdict_get_int(r, "return");
> +    qobject_unref(r);
> +    return clock_period;
> +}
> +
> +
> diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
> index 72a7823406..c0686c7b30 100644
> --- a/tests/qtest/stm32l4x5_gpio-test.c
> +++ b/tests/qtest/stm32l4x5_gpio-test.c
> @@ -10,6 +10,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "libqtest-single.h"
> +#include "stm32l4x5.h"
>  
>  #define GPIO_BASE_ADDR 0x48000000
>  #define GPIO_SIZE      0x400
> @@ -505,6 +506,26 @@ static void test_bsrr_brr(const void *data)
>      gpio_writel(gpio, ODR, reset(gpio, ODR));
>  }
>  
> +static void test_clock_enable(void)
> +{
> +    /*
> +     * For each GPIO, enable its clock in RCC
> +     * and check that its clock period changes to SYSCLK_PERIOD
> +     */
> +    unsigned int gpio_id;
> +
> +    for (uint32_t gpio = GPIO_A; gpio <= GPIO_H; gpio += GPIO_B - GPIO_A) {
> +        gpio_id = get_gpio_id(gpio);
> +        g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c/clk",
> +                                                gpio_id + 'a');
> +        g_assert_cmpuint(get_clock_period(global_qtest, path), ==, 0);
> +        /* Enable the gpio clock */
> +        writel(RCC_AHB2ENR, readl(RCC_AHB2ENR) | (0x1 << gpio_id));
> +        g_assert_cmpuint(get_clock_period(global_qtest, path), ==,
> +                         SYSCLK_PERIOD);
> +    }
> +}
> +
>  int main(int argc, char **argv)
>  {
>      int ret;
> @@ -556,6 +577,8 @@ int main(int argc, char **argv)
>      qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
>                          test_data(GPIO_D, 0),
>                          test_bsrr_brr);
> +    qtest_add_func("stm32l4x5/gpio/test_clock_enable",
> +                   test_clock_enable);
>  
>      qtest_start("-machine b-l475e-iot01a");
>      ret = g_test_run();
> diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
> index 506ca08bc2..8eaffe43ea 100644
> --- a/tests/qtest/stm32l4x5_syscfg-test.c
> +++ b/tests/qtest/stm32l4x5_syscfg-test.c
> @@ -10,6 +10,7 @@
>  
>  #include "qemu/osdep.h"
>  #include "libqtest-single.h"
> +#include "stm32l4x5.h"
>  
>  #define SYSCFG_BASE_ADDR 0x40010000
>  #define SYSCFG_MEMRMP 0x00
> @@ -26,7 +27,9 @@
>  #define INVALID_ADDR 0x2C
>  
>  /* SoC forwards GPIOs to SysCfg */
> -#define SYSCFG "/machine/soc"
> +#define SOC "/machine/soc"
> +#define SYSCFG "/machine/soc/syscfg"
> +#define SYSCFG_CLK "/machine/soc/syscfg/clk"
>  #define EXTI "/machine/soc/exti"
>  
>  static void syscfg_writel(unsigned int offset, uint32_t value)
> @@ -41,7 +44,7 @@ static uint32_t syscfg_readl(unsigned int offset)
>  
>  static void syscfg_set_irq(int num, int level)
>  {
> -   qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
> +   qtest_set_irq_in(global_qtest, SOC, NULL, num, level);
>  }
>  
>  static void system_reset(void)
> @@ -301,6 +304,17 @@ static void test_irq_gpio_multiplexer(void)
>      syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
>  }
>  
> +static void test_clock_enable(void)
> +{
> +    g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), ==, 0);
> +
> +    /* Enable SYSCFG clock */
> +    writel(RCC_APB2ENR, readl(RCC_APB2ENR) | (0x1 << 0));
> +
> +    g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), ==,
> +                                       SYSCLK_PERIOD);
> +}
> +
>  int main(int argc, char **argv)
>  {
>      int ret;
> @@ -325,6 +339,8 @@ int main(int argc, char **argv)
>                     test_irq_pin_multiplexer);
>      qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
>                     test_irq_gpio_multiplexer);
> +    qtest_add_func("stm32l4x5/syscfg/test_clock_enable",
> +                   test_clock_enable);
>  
>      qtest_start("-machine b-l475e-iot01a");
>      ret = g_test_run();
> diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usart-test.c
> index 8902518233..4bad3603e8 100644
> --- a/tests/qtest/stm32l4x5_usart-test.c
> +++ b/tests/qtest/stm32l4x5_usart-test.c
> @@ -12,6 +12,7 @@
>  #include "libqtest.h"
>  #include "hw/misc/stm32l4x5_rcc_internals.h"
>  #include "hw/registerfields.h"
> +#include "stm32l4x5.h"
>  
>  #define RCC_BASE_ADDR 0x40021000
>  /* Use USART 1 ADDR, assume the others work the same */
> @@ -296,6 +297,30 @@ static void test_send_str(void)
>      qtest_quit(qts);
>  }
>  
> +static void check_clock(QTestState *qts, const char *path, uint32_t rcc_reg,
> +                        uint32_t reg_offset)
> +{
> +    g_assert_cmpuint(get_clock_period(qts, path), ==, 0);
> +    qtest_writel(qts, rcc_reg, qtest_readl(qts, rcc_reg) | (0x1 << reg_offset));
> +    g_assert_cmpuint(get_clock_period(qts, path), ==, SYSCLK_PERIOD);
> +}
> +
> +static void test_clock_enable(void)
> +{
> +    /*
> +     * For each USART device, enable its clock in RCC
> +     * and check that its clock frequency is SYSCLK_PERIOD
> +     */
> +    QTestState *qts = qtest_init("-M b-l475e-iot01a");
> +
> +    check_clock(qts, "machine/soc/usart[0]/clk", RCC_APB2ENR, 14);
> +    check_clock(qts, "machine/soc/usart[1]/clk", RCC_APB1ENR1, 17);
> +    check_clock(qts, "machine/soc/usart[2]/clk", RCC_APB1ENR1, 18);
> +    check_clock(qts, "machine/soc/uart[0]/clk", RCC_APB1ENR1, 19);
> +    check_clock(qts, "machine/soc/uart[1]/clk", RCC_APB1ENR1, 20);
> +    check_clock(qts, "machine/soc/lpuart1/clk", RCC_APB1ENR2, 0);
> +}
> +
>  int main(int argc, char **argv)
>  {
>      int ret;
> @@ -308,6 +333,7 @@ int main(int argc, char **argv)
>      qtest_add_func("stm32l4x5/usart/send_char", test_send_char);
>      qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str);
>      qtest_add_func("stm32l4x5/usart/send_str", test_send_str);
> +    qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable);
>      ret = g_test_run();
>  
>      return ret;
> -- 
> 2.43.2
> 

--
diff mbox series

Patch

diff --git a/tests/qtest/stm32l4x5.h b/tests/qtest/stm32l4x5.h
new file mode 100644
index 0000000000..2d21cc666c
--- /dev/null
+++ b/tests/qtest/stm32l4x5.h
@@ -0,0 +1,42 @@ 
+/*
+ * QTest testcase header for STM32L4X5 :
+ * used for consolidating common objects in stm32l4x5_*-test.c
+ *
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqtest.h"
+
+/* copied from clock.h */
+#define CLOCK_PERIOD_1SEC (1000000000llu << 32)
+#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_PERIOD_1SEC / (hz) : 0u)
+/*
+ * MSI (4 MHz) is used as system clock source after startup
+ * from Reset.
+ * AHB, APB1 and APB2 prescalers are set to 1 at reset.
+ */
+#define SYSCLK_PERIOD CLOCK_PERIOD_FROM_HZ(4000000)
+#define RCC_AHB2ENR 0x4002104C
+#define RCC_APB1ENR1 0x40021058
+#define RCC_APB1ENR2 0x4002105C
+#define RCC_APB2ENR 0x40021060
+
+
+static inline uint64_t get_clock_period(QTestState *qts, const char *path)
+{
+    uint64_t clock_period = 0;
+    QDict *r;
+
+    r = qtest_qmp(qts, "{ 'execute': 'qom-get', 'arguments':"
+        " { 'path': %s, 'property': 'qtest-clock-period'} }", path);
+    g_assert_false(qdict_haskey(r, "error"));
+    clock_period = qdict_get_int(r, "return");
+    qobject_unref(r);
+    return clock_period;
+}
+
+
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
index 72a7823406..c0686c7b30 100644
--- a/tests/qtest/stm32l4x5_gpio-test.c
+++ b/tests/qtest/stm32l4x5_gpio-test.c
@@ -10,6 +10,7 @@ 
 
 #include "qemu/osdep.h"
 #include "libqtest-single.h"
+#include "stm32l4x5.h"
 
 #define GPIO_BASE_ADDR 0x48000000
 #define GPIO_SIZE      0x400
@@ -505,6 +506,26 @@  static void test_bsrr_brr(const void *data)
     gpio_writel(gpio, ODR, reset(gpio, ODR));
 }
 
+static void test_clock_enable(void)
+{
+    /*
+     * For each GPIO, enable its clock in RCC
+     * and check that its clock period changes to SYSCLK_PERIOD
+     */
+    unsigned int gpio_id;
+
+    for (uint32_t gpio = GPIO_A; gpio <= GPIO_H; gpio += GPIO_B - GPIO_A) {
+        gpio_id = get_gpio_id(gpio);
+        g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c/clk",
+                                                gpio_id + 'a');
+        g_assert_cmpuint(get_clock_period(global_qtest, path), ==, 0);
+        /* Enable the gpio clock */
+        writel(RCC_AHB2ENR, readl(RCC_AHB2ENR) | (0x1 << gpio_id));
+        g_assert_cmpuint(get_clock_period(global_qtest, path), ==,
+                         SYSCLK_PERIOD);
+    }
+}
+
 int main(int argc, char **argv)
 {
     int ret;
@@ -556,6 +577,8 @@  int main(int argc, char **argv)
     qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
                         test_data(GPIO_D, 0),
                         test_bsrr_brr);
+    qtest_add_func("stm32l4x5/gpio/test_clock_enable",
+                   test_clock_enable);
 
     qtest_start("-machine b-l475e-iot01a");
     ret = g_test_run();
diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
index 506ca08bc2..8eaffe43ea 100644
--- a/tests/qtest/stm32l4x5_syscfg-test.c
+++ b/tests/qtest/stm32l4x5_syscfg-test.c
@@ -10,6 +10,7 @@ 
 
 #include "qemu/osdep.h"
 #include "libqtest-single.h"
+#include "stm32l4x5.h"
 
 #define SYSCFG_BASE_ADDR 0x40010000
 #define SYSCFG_MEMRMP 0x00
@@ -26,7 +27,9 @@ 
 #define INVALID_ADDR 0x2C
 
 /* SoC forwards GPIOs to SysCfg */
-#define SYSCFG "/machine/soc"
+#define SOC "/machine/soc"
+#define SYSCFG "/machine/soc/syscfg"
+#define SYSCFG_CLK "/machine/soc/syscfg/clk"
 #define EXTI "/machine/soc/exti"
 
 static void syscfg_writel(unsigned int offset, uint32_t value)
@@ -41,7 +44,7 @@  static uint32_t syscfg_readl(unsigned int offset)
 
 static void syscfg_set_irq(int num, int level)
 {
-   qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
+   qtest_set_irq_in(global_qtest, SOC, NULL, num, level);
 }
 
 static void system_reset(void)
@@ -301,6 +304,17 @@  static void test_irq_gpio_multiplexer(void)
     syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
 }
 
+static void test_clock_enable(void)
+{
+    g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), ==, 0);
+
+    /* Enable SYSCFG clock */
+    writel(RCC_APB2ENR, readl(RCC_APB2ENR) | (0x1 << 0));
+
+    g_assert_cmpuint(get_clock_period(global_qtest, SYSCFG_CLK), ==,
+                                       SYSCLK_PERIOD);
+}
+
 int main(int argc, char **argv)
 {
     int ret;
@@ -325,6 +339,8 @@  int main(int argc, char **argv)
                    test_irq_pin_multiplexer);
     qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
                    test_irq_gpio_multiplexer);
+    qtest_add_func("stm32l4x5/syscfg/test_clock_enable",
+                   test_clock_enable);
 
     qtest_start("-machine b-l475e-iot01a");
     ret = g_test_run();
diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usart-test.c
index 8902518233..4bad3603e8 100644
--- a/tests/qtest/stm32l4x5_usart-test.c
+++ b/tests/qtest/stm32l4x5_usart-test.c
@@ -12,6 +12,7 @@ 
 #include "libqtest.h"
 #include "hw/misc/stm32l4x5_rcc_internals.h"
 #include "hw/registerfields.h"
+#include "stm32l4x5.h"
 
 #define RCC_BASE_ADDR 0x40021000
 /* Use USART 1 ADDR, assume the others work the same */
@@ -296,6 +297,30 @@  static void test_send_str(void)
     qtest_quit(qts);
 }
 
+static void check_clock(QTestState *qts, const char *path, uint32_t rcc_reg,
+                        uint32_t reg_offset)
+{
+    g_assert_cmpuint(get_clock_period(qts, path), ==, 0);
+    qtest_writel(qts, rcc_reg, qtest_readl(qts, rcc_reg) | (0x1 << reg_offset));
+    g_assert_cmpuint(get_clock_period(qts, path), ==, SYSCLK_PERIOD);
+}
+
+static void test_clock_enable(void)
+{
+    /*
+     * For each USART device, enable its clock in RCC
+     * and check that its clock frequency is SYSCLK_PERIOD
+     */
+    QTestState *qts = qtest_init("-M b-l475e-iot01a");
+
+    check_clock(qts, "machine/soc/usart[0]/clk", RCC_APB2ENR, 14);
+    check_clock(qts, "machine/soc/usart[1]/clk", RCC_APB1ENR1, 17);
+    check_clock(qts, "machine/soc/usart[2]/clk", RCC_APB1ENR1, 18);
+    check_clock(qts, "machine/soc/uart[0]/clk", RCC_APB1ENR1, 19);
+    check_clock(qts, "machine/soc/uart[1]/clk", RCC_APB1ENR1, 20);
+    check_clock(qts, "machine/soc/lpuart1/clk", RCC_APB1ENR2, 0);
+}
+
 int main(int argc, char **argv)
 {
     int ret;
@@ -308,6 +333,7 @@  int main(int argc, char **argv)
     qtest_add_func("stm32l4x5/usart/send_char", test_send_char);
     qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str);
     qtest_add_func("stm32l4x5/usart/send_str", test_send_str);
+    qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable);
     ret = g_test_run();
 
     return ret;