| Message ID | 20240627100053.150937-1-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 6/27/24 03:00, Alistair Francis wrote: > The following changes since commit 3f044554b94fc0756d5b3cdbf84501e0eea0e629: > > Merge tag 'pull-vfio-20240624' ofhttps://github.com/legoater/qemu into staging (2024-06-24 21:30:34 -0700) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240627-1 > > for you to fetch changes up to 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7: > > target/riscv: Apply modularized matching conditions for icount trigger (2024-06-27 13:09:16 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.1 > > * Extend virtual irq csrs masks to be 64 bit wide > * Move Guest irqs out of the core local irqs range > * zvbb implies zvkb > * virt: add address-cells in create_fdt_one_aplic() > * virt: add aplic nodename helper > * virt: rename aplic nodename to 'interrupt-controller' > * virt: aplic DT: add 'qemu, aplic' to 'compatible' > * virt: aplic DT: rename prop to 'riscv, delegation' > * virt: change imsic nodename to 'interrupt-controller' > * virt: imsics DT: add 'qemu, imsics' to 'compatible' > * virt: imsics DT: add '#msi-cells' > * QEMU support for KVM Guest Debug on RISC-V > * Support RISC-V privilege 1.13 spec > * Add support for RISC-V ACPI tests > * Modularize common match conditions for trigger Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
The following changes since commit 3f044554b94fc0756d5b3cdbf84501e0eea0e629: Merge tag 'pull-vfio-20240624' of https://github.com/legoater/qemu into staging (2024-06-24 21:30:34 -0700) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240627-1 for you to fetch changes up to 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7: target/riscv: Apply modularized matching conditions for icount trigger (2024-06-27 13:09:16 +1000) ---------------------------------------------------------------- RISC-V PR for 9.1 * Extend virtual irq csrs masks to be 64 bit wide * Move Guest irqs out of the core local irqs range * zvbb implies zvkb * virt: add address-cells in create_fdt_one_aplic() * virt: add aplic nodename helper * virt: rename aplic nodename to 'interrupt-controller' * virt: aplic DT: add 'qemu, aplic' to 'compatible' * virt: aplic DT: rename prop to 'riscv, delegation' * virt: change imsic nodename to 'interrupt-controller' * virt: imsics DT: add 'qemu, imsics' to 'compatible' * virt: imsics DT: add '#msi-cells' * QEMU support for KVM Guest Debug on RISC-V * Support RISC-V privilege 1.13 spec * Add support for RISC-V ACPI tests * Modularize common match conditions for trigger ---------------------------------------------------------------- Alvin Chang (3): target/riscv: Add functions for common matching conditions of trigger target/riscv: Apply modularized matching conditions for watchpoint target/riscv: Apply modularized matching conditions for icount trigger Branislav Brzak (1): target/riscv: Fix froundnx.h nanbox check Chao Du (3): target/riscv/kvm: add software breakpoints support target/riscv/kvm: handle the exit with debug reason target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG Clément Léger (1): target/riscv: fix instructions count handling in icount mode Daniel Henrique Barboza (8): hw/riscv/virt.c: add address-cells in create_fdt_one_aplic() hw/riscv/virt.c: add aplic nodename helper hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller' hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible' hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation' hw/riscv/virt.c: change imsic nodename to 'interrupt-controller' hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible' hw/riscv/virt.c: imsics DT: add '#msi-cells' Fea.Wang (5): target/riscv: Define macros and variables for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support the version for ss1p13 Frank Chang (6): target/riscv: Introduce extension implied rules definition target/riscv: Introduce extension implied rule helpers target/riscv: Add MISA extension implied rules target/riscv: Add multi extension implied rules target/riscv: Add Zc extension implied rule target/riscv: Remove extension auto-update check statements Jerry Zhang Jian (1): target/riscv: zvbb implies zvkb Jim Shu (1): target/riscv: Reuse the conversion function of priv_spec Rajnesh Kanwal (2): target/riscv: Extend virtual irq csrs masks to be 64 bit wide. target/riscv: Move Guest irqs out of the core local irqs range. Sunil V L (1): hw/riscv/virt.c: Make block devices default to virtio configs/targets/riscv64-softmmu.mak | 1 + include/hw/riscv/virt.h | 1 + target/riscv/cpu.h | 28 ++- target/riscv/cpu_bits.h | 8 +- target/riscv/cpu_cfg.h | 1 + hw/riscv/virt.c | 38 +++- target/riscv/cpu.c | 404 +++++++++++++++++++++++++++++++++++- target/riscv/csr.c | 92 ++++++-- target/riscv/debug.c | 129 ++++++++---- target/riscv/fpu_helper.c | 2 +- target/riscv/kvm/kvm-cpu.c | 89 ++++++++ target/riscv/tcg/tcg-cpu.c | 287 ++++++++++++++----------- 12 files changed, 877 insertions(+), 203 deletions(-)