| Message ID | 20240704082922.1464317-3-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support AST2700 network | expand |
On 7/4/24 10:29 AM, Jamin Lin wrote: > Update TX and RX ring base address data type to uint64_t for > 64 bits dram address DMA support. > > Both "Normal Priority Transmit Ring Base Address Register(0x20)" and > "Receive Ring Base Address Register (0x24)" are used for saving the > low part physical address of descriptor manager. > > Therefore, changes to set TX and RX descriptor manager address bits [31:0] > in ftgmac100_read and ftgmac100_write functions. > > Incrementing the version of vmstate to 2. > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > hw/net/ftgmac100.c | 33 ++++++++++++++++----------------- > include/hw/net/ftgmac100.h | 9 ++++----- > 2 files changed, 20 insertions(+), 22 deletions(-) > > diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c > index 9e1f12cd33..d026242e2b 100644 > --- a/hw/net/ftgmac100.c > +++ b/hw/net/ftgmac100.c > @@ -515,12 +515,12 @@ out: > return frame_size; > } > > -static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring, > - uint32_t tx_descriptor) > +static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring, > + uint64_t tx_descriptor) > { > int frame_size = 0; > uint8_t *ptr = s->frame; > - uint32_t addr = tx_descriptor; > + uint64_t addr = tx_descriptor; > uint32_t flags = 0; > > while (1) { > @@ -726,9 +726,9 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size) > case FTGMAC100_MATH1: > return s->math[1]; > case FTGMAC100_RXR_BADR: > - return s->rx_ring; > + return extract64(s->rx_ring, 0, 32); > case FTGMAC100_NPTXR_BADR: > - return s->tx_ring; > + return extract64(s->tx_ring, 0, 32); > case FTGMAC100_ITC: > return s->itc; > case FTGMAC100_DBLAC: > @@ -799,9 +799,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr, > HWADDR_PRIx "\n", __func__, value); > return; > } > - > - s->rx_ring = value; > - s->rx_descriptor = s->rx_ring; > + s->rx_ring = deposit64(s->rx_ring, 0, 32, value); > + s->rx_descriptor = deposit64(s->rx_descriptor, 0, 32, value); > break; > > case FTGMAC100_RBSR: /* DMA buffer size */ > @@ -814,8 +813,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr, > HWADDR_PRIx "\n", __func__, value); > return; > } > - s->tx_ring = value; > - s->tx_descriptor = s->tx_ring; > + s->tx_ring = deposit64(s->tx_ring, 0, 32, value); > + s->tx_descriptor = deposit64(s->tx_descriptor, 0, 32, value); > break; > > case FTGMAC100_NPTXPD: /* Trigger transmit */ > @@ -957,7 +956,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf, > FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); > FTGMAC100Desc bd; > uint32_t flags = 0; > - uint32_t addr; > + uint64_t addr; > uint32_t crc; > uint32_t buf_addr; > uint8_t *crc_ptr; > @@ -1126,18 +1125,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp) > > static const VMStateDescription vmstate_ftgmac100 = { > .name = TYPE_FTGMAC100, > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (const VMStateField[]) { > VMSTATE_UINT32(irq_state, FTGMAC100State), > VMSTATE_UINT32(isr, FTGMAC100State), > VMSTATE_UINT32(ier, FTGMAC100State), > VMSTATE_UINT32(rx_enabled, FTGMAC100State), > - VMSTATE_UINT32(rx_ring, FTGMAC100State), > VMSTATE_UINT32(rbsr, FTGMAC100State), > - VMSTATE_UINT32(tx_ring, FTGMAC100State), > - VMSTATE_UINT32(rx_descriptor, FTGMAC100State), > - VMSTATE_UINT32(tx_descriptor, FTGMAC100State), > VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2), > VMSTATE_UINT32(itc, FTGMAC100State), > VMSTATE_UINT32(aptcr, FTGMAC100State), > @@ -1156,6 +1151,10 @@ static const VMStateDescription vmstate_ftgmac100 = { > VMSTATE_UINT32(phy_int_mask, FTGMAC100State), > VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), > VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), > + VMSTATE_UINT64(rx_ring, FTGMAC100State), > + VMSTATE_UINT64(tx_ring, FTGMAC100State), > + VMSTATE_UINT64(rx_descriptor, FTGMAC100State), > + VMSTATE_UINT64(tx_descriptor, FTGMAC100State), > VMSTATE_END_OF_LIST() > } > }; > diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h > index 269446e858..aae57ae8cb 100644 > --- a/include/hw/net/ftgmac100.h > +++ b/include/hw/net/ftgmac100.h > @@ -42,10 +42,6 @@ struct FTGMAC100State { > uint32_t isr; > uint32_t ier; > uint32_t rx_enabled; > - uint32_t rx_ring; > - uint32_t rx_descriptor; > - uint32_t tx_ring; > - uint32_t tx_descriptor; > uint32_t math[2]; > uint32_t rbsr; > uint32_t itc; > @@ -58,7 +54,10 @@ struct FTGMAC100State { > uint32_t phycr; > uint32_t phydata; > uint32_t fcr; > - > + uint64_t rx_ring; > + uint64_t rx_descriptor; > + uint64_t tx_ring; > + uint64_t tx_descriptor; > > uint32_t phy_status; > uint32_t phy_control;
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index 9e1f12cd33..d026242e2b 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -515,12 +515,12 @@ out: return frame_size; } -static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring, - uint32_t tx_descriptor) +static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring, + uint64_t tx_descriptor) { int frame_size = 0; uint8_t *ptr = s->frame; - uint32_t addr = tx_descriptor; + uint64_t addr = tx_descriptor; uint32_t flags = 0; while (1) { @@ -726,9 +726,9 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size) case FTGMAC100_MATH1: return s->math[1]; case FTGMAC100_RXR_BADR: - return s->rx_ring; + return extract64(s->rx_ring, 0, 32); case FTGMAC100_NPTXR_BADR: - return s->tx_ring; + return extract64(s->tx_ring, 0, 32); case FTGMAC100_ITC: return s->itc; case FTGMAC100_DBLAC: @@ -799,9 +799,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr, HWADDR_PRIx "\n", __func__, value); return; } - - s->rx_ring = value; - s->rx_descriptor = s->rx_ring; + s->rx_ring = deposit64(s->rx_ring, 0, 32, value); + s->rx_descriptor = deposit64(s->rx_descriptor, 0, 32, value); break; case FTGMAC100_RBSR: /* DMA buffer size */ @@ -814,8 +813,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr, HWADDR_PRIx "\n", __func__, value); return; } - s->tx_ring = value; - s->tx_descriptor = s->tx_ring; + s->tx_ring = deposit64(s->tx_ring, 0, 32, value); + s->tx_descriptor = deposit64(s->tx_descriptor, 0, 32, value); break; case FTGMAC100_NPTXPD: /* Trigger transmit */ @@ -957,7 +956,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf, FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); FTGMAC100Desc bd; uint32_t flags = 0; - uint32_t addr; + uint64_t addr; uint32_t crc; uint32_t buf_addr; uint8_t *crc_ptr; @@ -1126,18 +1125,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp) static const VMStateDescription vmstate_ftgmac100 = { .name = TYPE_FTGMAC100, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (const VMStateField[]) { VMSTATE_UINT32(irq_state, FTGMAC100State), VMSTATE_UINT32(isr, FTGMAC100State), VMSTATE_UINT32(ier, FTGMAC100State), VMSTATE_UINT32(rx_enabled, FTGMAC100State), - VMSTATE_UINT32(rx_ring, FTGMAC100State), VMSTATE_UINT32(rbsr, FTGMAC100State), - VMSTATE_UINT32(tx_ring, FTGMAC100State), - VMSTATE_UINT32(rx_descriptor, FTGMAC100State), - VMSTATE_UINT32(tx_descriptor, FTGMAC100State), VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2), VMSTATE_UINT32(itc, FTGMAC100State), VMSTATE_UINT32(aptcr, FTGMAC100State), @@ -1156,6 +1151,10 @@ static const VMStateDescription vmstate_ftgmac100 = { VMSTATE_UINT32(phy_int_mask, FTGMAC100State), VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), + VMSTATE_UINT64(rx_ring, FTGMAC100State), + VMSTATE_UINT64(tx_ring, FTGMAC100State), + VMSTATE_UINT64(rx_descriptor, FTGMAC100State), + VMSTATE_UINT64(tx_descriptor, FTGMAC100State), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h index 269446e858..aae57ae8cb 100644 --- a/include/hw/net/ftgmac100.h +++ b/include/hw/net/ftgmac100.h @@ -42,10 +42,6 @@ struct FTGMAC100State { uint32_t isr; uint32_t ier; uint32_t rx_enabled; - uint32_t rx_ring; - uint32_t rx_descriptor; - uint32_t tx_ring; - uint32_t tx_descriptor; uint32_t math[2]; uint32_t rbsr; uint32_t itc; @@ -58,7 +54,10 @@ struct FTGMAC100State { uint32_t phycr; uint32_t phydata; uint32_t fcr; - + uint64_t rx_ring; + uint64_t rx_descriptor; + uint64_t tx_ring; + uint64_t tx_descriptor; uint32_t phy_status; uint32_t phy_control;
Update TX and RX ring base address data type to uint64_t for 64 bits dram address DMA support. Both "Normal Priority Transmit Ring Base Address Register(0x20)" and "Receive Ring Base Address Register (0x24)" are used for saving the low part physical address of descriptor manager. Therefore, changes to set TX and RX descriptor manager address bits [31:0] in ftgmac100_read and ftgmac100_write functions. Incrementing the version of vmstate to 2. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/net/ftgmac100.c | 33 ++++++++++++++++----------------- include/hw/net/ftgmac100.h | 9 ++++----- 2 files changed, 20 insertions(+), 22 deletions(-)