diff mbox series

[v1,3/3] intel_iommu: Bypass barrier wait descriptor

Message ID 20240704144737.996889-4-clement.mathieu--drif@eviden.com (mailing list archive)
State New, archived
Headers show
Series VT-d minor fixes | expand

Commit Message

CLEMENT MATHIEU--DRIF July 4, 2024, 2:48 p.m. UTC 
From: Clement Mathieu--Drif <cmdetu@gmail.com>

wait_desc with SW=0,IF=0,FN=1 must not be considered as an
invalid descriptor as it is used to implement section 7.10 of
the VT-d spec

Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
---
 hw/i386/intel_iommu.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index be0cb39b5c..12ea3a9aa0 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2561,6 +2561,12 @@  static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
     } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
         /* Interrupt flag */
         vtd_generate_completion_event(s);
+    } else if (inv_desc->lo & VTD_INV_DESC_WAIT_FN) {
+        /*
+         * SW = 0, IF = 0, FN = 1
+         * This kind of descriptor is defined in section 7.10 of VT-d
+         * Nothing to do as we process the events sequentially
+         */
     } else {
         error_report_once("%s: invalid wait desc: hi=%"PRIx64", lo=%"PRIx64
                           " (unknown type)", __func__, inv_desc->hi,