diff mbox series

[v2,03/13] target/riscv: Enable S*stateen bits for AIA

Message ID 20240723-counter_delegation-v2-3-c4170a5348ca@rivosinc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V Counter delegation ISA extension support | expand

Commit Message

Atish Kumar Patra July 23, 2024, 11:30 p.m. UTC 
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
access.

Bit 60 controls the indirect CSRs
Bit 59 controls the most AIA CSR state
Bit 58 controls the IMSIC state such as stopei and vstopei

Enable the corresponding bits in [m|h]stateen and enable corresponding
checks in the CSR accessor functions.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 87 insertions(+), 1 deletion(-)

Comments

Alistair Francis Aug. 6, 2024, 12:12 a.m. UTC | #1 
On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
> access.
>
> Bit 60 controls the indirect CSRs
> Bit 59 controls the most AIA CSR state
> Bit 58 controls the IMSIC state such as stopei and vstopei
>
> Enable the corresponding bits in [m|h]stateen and enable corresponding
> checks in the CSR accessor functions.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  target/riscv/csr.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 87 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 58be8bc3cc8c..18b9ae802b15 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -316,19 +316,42 @@ static RISCVException smode32(CPURISCVState *env, int csrno)
>
>  static RISCVException aia_smode(CPURISCVState *env, int csrno)
>  {
> +    int ret;
> +
>      if (!riscv_cpu_cfg(env)->ext_ssaia) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> +    if (csrno == CSR_STOPEI) {
> +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
> +    } else {
> +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> +    }
> +
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
>      return smode(env, csrno);
>  }
>
>  static RISCVException aia_smode32(CPURISCVState *env, int csrno)
>  {
> +    int ret;
> +
>      if (!riscv_cpu_cfg(env)->ext_ssaia) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
>      return smode32(env, csrno);
>  }
>
> @@ -567,15 +590,38 @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
>
>  static RISCVException aia_hmode(CPURISCVState *env, int csrno)
>  {
> +    int ret;
> +
>      if (!riscv_cpu_cfg(env)->ext_ssaia) {
>          return RISCV_EXCP_ILLEGAL_INST;
>       }
>
> -     return hmode(env, csrno);
> +    if (csrno == CSR_VSTOPEI) {
> +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
> +    } else {
> +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> +    }
> +
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
> +    return hmode(env, csrno);
>  }
>
>  static RISCVException aia_hmode32(CPURISCVState *env, int csrno)
>  {
> +    int ret;
> +
> +    if (!riscv_cpu_cfg(env)->ext_ssaia) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +     }
> +
> +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
>      if (!riscv_cpu_cfg(env)->ext_ssaia) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
> @@ -1992,6 +2038,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
>                                     target_ulong wr_mask)
>  {
>      target_ulong *iselect;
> +    int ret;
> +
> +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
>
>      /* Translate CSR number for VS-mode */
>      csrno = csrind_xlate_vs_csrno(env, csrno);
> @@ -2162,6 +2214,11 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
>      int ret = -EINVAL;
>      target_ulong isel;
>
> +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
> +    if (ret != RISCV_EXCP_NONE) {
> +        return ret;
> +    }
> +
>      /* Translate CSR number for VS-mode */
>      csrno = csrind_xlate_vs_csrno(env, csrno);
>
> @@ -2610,6 +2667,22 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
>      if (env->priv_ver >= PRIV_VERSION_1_13_0) {
>          wr_mask |= SMSTATEEN0_P1P13;
>      }
> +    /*
> +     * TODO: Do we need to check ssaia as well ? Can we enable ssaia without
> +     * smaia ?
> +     */
> +    if (riscv_cpu_cfg(env)->ext_smaia) {
> +        wr_mask |= SMSTATEEN0_SVSLCT;
> +    }

This looks right to me, do we need the TODO?

Otherwise

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair
Atish Kumar Patra Aug. 7, 2024, 7:53 a.m. UTC | #2 
On Mon, Aug 5, 2024 at 5:12 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
> > access.
> >
> > Bit 60 controls the indirect CSRs
> > Bit 59 controls the most AIA CSR state
> > Bit 58 controls the IMSIC state such as stopei and vstopei
> >
> > Enable the corresponding bits in [m|h]stateen and enable corresponding
> > checks in the CSR accessor functions.
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> >  target/riscv/csr.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 87 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 58be8bc3cc8c..18b9ae802b15 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -316,19 +316,42 @@ static RISCVException smode32(CPURISCVState *env, int csrno)
> >
> >  static RISCVException aia_smode(CPURISCVState *env, int csrno)
> >  {
> > +    int ret;
> > +
> >      if (!riscv_cpu_cfg(env)->ext_ssaia) {
> >          return RISCV_EXCP_ILLEGAL_INST;
> >      }
> >
> > +    if (csrno == CSR_STOPEI) {
> > +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
> > +    } else {
> > +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> > +    }
> > +
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> >      return smode(env, csrno);
> >  }
> >
> >  static RISCVException aia_smode32(CPURISCVState *env, int csrno)
> >  {
> > +    int ret;
> > +
> >      if (!riscv_cpu_cfg(env)->ext_ssaia) {
> >          return RISCV_EXCP_ILLEGAL_INST;
> >      }
> >
> > +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> >      return smode32(env, csrno);
> >  }
> >
> > @@ -567,15 +590,38 @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> >
> >  static RISCVException aia_hmode(CPURISCVState *env, int csrno)
> >  {
> > +    int ret;
> > +
> >      if (!riscv_cpu_cfg(env)->ext_ssaia) {
> >          return RISCV_EXCP_ILLEGAL_INST;
> >       }
> >
> > -     return hmode(env, csrno);
> > +    if (csrno == CSR_VSTOPEI) {
> > +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
> > +    } else {
> > +        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> > +    }
> > +
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> > +    return hmode(env, csrno);
> >  }
> >
> >  static RISCVException aia_hmode32(CPURISCVState *env, int csrno)
> >  {
> > +    int ret;
> > +
> > +    if (!riscv_cpu_cfg(env)->ext_ssaia) {
> > +        return RISCV_EXCP_ILLEGAL_INST;
> > +     }
> > +
> > +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> >      if (!riscv_cpu_cfg(env)->ext_ssaia) {
> >          return RISCV_EXCP_ILLEGAL_INST;
> >      }
> > @@ -1992,6 +2038,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
> >                                     target_ulong wr_mask)
> >  {
> >      target_ulong *iselect;
> > +    int ret;
> > +
> > +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> >
> >      /* Translate CSR number for VS-mode */
> >      csrno = csrind_xlate_vs_csrno(env, csrno);
> > @@ -2162,6 +2214,11 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
> >      int ret = -EINVAL;
> >      target_ulong isel;
> >
> > +    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
> > +    if (ret != RISCV_EXCP_NONE) {
> > +        return ret;
> > +    }
> > +
> >      /* Translate CSR number for VS-mode */
> >      csrno = csrind_xlate_vs_csrno(env, csrno);
> >
> > @@ -2610,6 +2667,22 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
> >      if (env->priv_ver >= PRIV_VERSION_1_13_0) {
> >          wr_mask |= SMSTATEEN0_P1P13;
> >      }
> > +    /*
> > +     * TODO: Do we need to check ssaia as well ? Can we enable ssaia without
> > +     * smaia ?
> > +     */
> > +    if (riscv_cpu_cfg(env)->ext_smaia) {
> > +        wr_mask |= SMSTATEEN0_SVSLCT;
> > +    }
>
> This looks right to me, do we need the TODO?
>

cool. I will remove the TODO.

> Otherwise
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58be8bc3cc8c..18b9ae802b15 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -316,19 +316,42 @@  static RISCVException smode32(CPURISCVState *env, int csrno)
 
 static RISCVException aia_smode(CPURISCVState *env, int csrno)
 {
+    int ret;
+
     if (!riscv_cpu_cfg(env)->ext_ssaia) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
+    if (csrno == CSR_STOPEI) {
+        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
+    } else {
+        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
+    }
+
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     return smode(env, csrno);
 }
 
 static RISCVException aia_smode32(CPURISCVState *env, int csrno)
 {
+    int ret;
+
     if (!riscv_cpu_cfg(env)->ext_ssaia) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     return smode32(env, csrno);
 }
 
@@ -567,15 +590,38 @@  static RISCVException pointer_masking(CPURISCVState *env, int csrno)
 
 static RISCVException aia_hmode(CPURISCVState *env, int csrno)
 {
+    int ret;
+
     if (!riscv_cpu_cfg(env)->ext_ssaia) {
         return RISCV_EXCP_ILLEGAL_INST;
      }
 
-     return hmode(env, csrno);
+    if (csrno == CSR_VSTOPEI) {
+        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
+    } else {
+        ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
+    }
+
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return hmode(env, csrno);
 }
 
 static RISCVException aia_hmode32(CPURISCVState *env, int csrno)
 {
+    int ret;
+
+    if (!riscv_cpu_cfg(env)->ext_ssaia) {
+        return RISCV_EXCP_ILLEGAL_INST;
+     }
+
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     if (!riscv_cpu_cfg(env)->ext_ssaia) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
@@ -1992,6 +2038,12 @@  static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
                                    target_ulong wr_mask)
 {
     target_ulong *iselect;
+    int ret;
+
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
 
     /* Translate CSR number for VS-mode */
     csrno = csrind_xlate_vs_csrno(env, csrno);
@@ -2162,6 +2214,11 @@  static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
     int ret = -EINVAL;
     target_ulong isel;
 
+    ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
     /* Translate CSR number for VS-mode */
     csrno = csrind_xlate_vs_csrno(env, csrno);
 
@@ -2610,6 +2667,22 @@  static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
     if (env->priv_ver >= PRIV_VERSION_1_13_0) {
         wr_mask |= SMSTATEEN0_P1P13;
     }
+    /*
+     * TODO: Do we need to check ssaia as well ? Can we enable ssaia without
+     * smaia ?
+     */
+    if (riscv_cpu_cfg(env)->ext_smaia) {
+        wr_mask |= SMSTATEEN0_SVSLCT;
+    }
+
+    /*
+     * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMSIC is
+     * implemented. However, that information is with MachineState and we can't
+     * figure that out in csr.c. Just enable if Smaia is available.
+     */
+    if (riscv_cpu_cfg(env)->ext_smaia) {
+        wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
+    }
 
     return write_mstateen(env, csrno, wr_mask, new_val);
 }
@@ -2691,6 +2764,19 @@  static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
         wr_mask |= SMSTATEEN0_FCSR;
     }
 
+    if (riscv_cpu_cfg(env)->ext_ssaia) {
+        wr_mask |= SMSTATEEN0_SVSLCT;
+    }
+
+    /*
+     * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMSIC is
+     * implemented. However, that information is with MachineState and we can't
+     * figure that out in csr.c. Just enable if Ssaia is available.
+     */
+    if (riscv_cpu_cfg(env)->ext_ssaia) {
+        wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
+    }
+
     return write_hstateen(env, csrno, wr_mask, new_val);
 }