From patchwork Fri Aug 9 08:12:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommy Wu X-Patchwork-Id: 13758513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABE82C52D71 for ; Fri, 9 Aug 2024 08:13:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1scKjr-0005lf-Qf; Fri, 09 Aug 2024 04:12:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1scKjq-0005gp-Kc for qemu-devel@nongnu.org; Fri, 09 Aug 2024 04:12:42 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1scKjo-0006nH-9G for qemu-devel@nongnu.org; Fri, 09 Aug 2024 04:12:42 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1fd9e6189d5so17014615ad.3 for ; Fri, 09 Aug 2024 01:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1723191158; x=1723795958; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1oI6nGeEdG0xhvDYynLlNJXm9hUsd9zbhDLS15UCJSI=; b=DzAJPKYUZUrwBHHrtHwQhPMR4u8FhUturkqRmPNlXqQJGnR+jc6EKpW5N0Ei1WavaH 593Hu44UiTKwjfTshIafK1nlIbqMXjLVOdsWIduyLzVQjaLX10FKLP/azOHW81FsTMjo B7QtByV0pe2O8SAbQbdvip+h/U7vdGaddeS10EtuJIzFQZeTB2bcnGTuc7WTQF9z+oii +/gUea9bdLbs8Vody3rMs+JJAWZTOSpXdazPcPqaX1zrfHOUbfBe08uHuQhtzZ4QuuxL i3uN5pRWPap/nK7U57XBGM8u2bez4ZlYcqJyGCzTFzBaeiXd62HsLenv5B1fyRRueKNp 3oNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723191158; x=1723795958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1oI6nGeEdG0xhvDYynLlNJXm9hUsd9zbhDLS15UCJSI=; b=NyAYRGQg5yNVbhjnWDuEhKyFI1pscmMKGGbkiRPt+jh0X+Sd7HDRoxQVxKMRnIWY+u U3mg6BKpnviDedRMxbFPdl/FNuTNY8VjODtLgO2i9b5dTKDeEpdQsmQryIAWBD59KO6+ 7W5jCxuRFuLrT6hGkWAUKFBsMW8naTUxB5moEmKmGSbv4UEoGLmCzt0GXCnffiwX0Zz3 kZr9YvMmh4nHc5o2IpbMsAZvWjgjU1IRrZKgqqPNQAc/5YpdpMWPUsqyCIQO/WKVimRF dI5yPadKcSae5E03AiHaWgzH7+LoqgOmu4Lk8wY3IXvuchwu4j5vVAfWJHliC9qedE1h bo9Q== X-Gm-Message-State: AOJu0YzNjBXPfCSjquJvcMVCEqG8NGtznCwtp7mf/Gkwsc5+p93g7pZ1 Yd/Os237XmWcR423HhV2mlfkq+iUP8jdR99Io4K8yntLAnw4ifwV1FqnaKC5OwBr0q38SQzE03m 3zibP5Gxi2ICzfO6DTzvt7lzp/aPbe/iRc66LdysNjhDxA61dlNGAkYPnWllmKwBMZfdxw+7i72 GKGNcJjvBTJPor3bC40qsG7rEa+CVYb7gn0JKcKQ== X-Google-Smtp-Source: AGHT+IEvWikipzIgptNoqiWFRjklKZRsP52KR1OSpqHYTmgAx82bX/n29/BzbehKdbeTWqtLuHiLkQ== X-Received: by 2002:a17:902:e845:b0:1fd:9e88:e4b7 with SMTP id d9443c01a7336-200ae4dbc2bmr6875895ad.12.1723191158135; Fri, 09 Aug 2024 01:12:38 -0700 (PDT) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff592b6cfbsm136391185ad.306.2024.08.09.01.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Aug 2024 01:12:37 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, Tommy Wu Subject: [PATCH v5 3/5] target/riscv: Add Smrnmi CSRs. Date: Fri, 9 Aug 2024 01:12:25 -0700 Message-Id: <20240809081227.1588508-4-tommy.wu@sifive.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240809081227.1588508-1-tommy.wu@sifive.com> References: <20240809081227.1588508-1-tommy.wu@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=tommy.wu@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Smrnmi extension adds the `MNSCRATCH`, `MNEPC`, `MNCAUSE`, `MNSTATUS` CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2f64b3df22..98e6940e93 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1024,6 +1024,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) riscv_trigger_reset_hold(env); } + if (cpu->cfg.ext_smrnmi) { + env->rnmip = 0; + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d8ad04ec31..a84e719d3f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,10 @@ struct CPUArchState { #endif /* CONFIG_KVM */ /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; target_ulong rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index e14b654c35..da1723496c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -350,6 +350,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -627,6 +633,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea3560342c..e5de72453c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -578,6 +578,17 @@ static RISCVException debug(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif static RISCVException seed(CPURISCVState *env, int csrno) @@ -4566,6 +4577,67 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch = val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc = val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause = val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask = (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |= MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus = (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif /* Crypto Extension */ @@ -5070,6 +5142,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_sstateen_1_3, .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* RNMI */ + [CSR_MNSCRATCH] = { "mnscratch", rnmi, read_mnscratch, write_mnscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNEPC] = { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNCAUSE] = { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNSTATUS] = { "mnstatus", rnmi, read_mnstatus, write_mnstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 },