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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53200f42667sm739978e87.294.2024.08.12.06.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Aug 2024 06:06:28 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Cc: sstabellini@kernel.org, anthony@xenproject.org, paul@xen.org, peter.maydell@linaro.org, alex.bennee@linaro.org, xenia.ragiadakou@amd.com, jason.andryuk@amd.com, edgar.iglesias@amd.com, xen-devel@lists.xenproject.org, "Edgar E. Iglesias" Subject: [PATCH v1 08/10] hw/xen: pvh-common: Add support for creating PCIe/GPEX Date: Mon, 12 Aug 2024 15:06:03 +0200 Message-ID: <20240812130606.90410-9-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240812130606.90410-1-edgar.iglesias@gmail.com> References: <20240812130606.90410-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Add support for optionally creating a PCIe/GPEX controller. Signed-off-by: Edgar E. Iglesias --- hw/xen/xen-pvh-common.c | 66 +++++++++++++++++++++++++++++++++ include/hw/xen/xen-pvh-common.h | 10 ++++- 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c index 69a2dbdb6d..b1432e4bd9 100644 --- a/hw/xen/xen-pvh-common.c +++ b/hw/xen/xen-pvh-common.c @@ -120,6 +120,59 @@ static void xen_enable_tpm(XenPVHCommonState *s) } #endif +static void xen_set_pci_intx_irq(void *opaque, int irq, int level) +{ + if (xen_set_pci_intx_level(xen_domid, 0, 0, 0, irq, level)) { + error_report("xendevicemodel_set_pci_intx_level failed"); + } +} + +static inline void xenpvh_gpex_init(XenPVHCommonState *s, + MemoryRegion *sysmem, + hwaddr ecam_base, hwaddr ecam_size, + hwaddr mmio_base, hwaddr mmio_size, + hwaddr mmio_high_base, + hwaddr mmio_high_size, + int intx_irq_base) +{ + MemoryRegion *ecam_reg; + MemoryRegion *mmio_reg; + DeviceState *dev; + int i; + + object_initialize_child(OBJECT(s), "gpex", &s->pci.gpex, + TYPE_GPEX_HOST); + dev = DEVICE(&s->pci.gpex); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(sysmem, ecam_base, ecam_reg); + + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + + if (mmio_size) { + memory_region_init_alias(&s->pci.mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, mmio_base, mmio_size); + memory_region_add_subregion(sysmem, mmio_base, &s->pci.mmio_alias); + } + + if (mmio_high_size) { + memory_region_init_alias(&s->pci.mmio_high_alias, OBJECT(dev), + "pcie-mmio-high", + mmio_reg, mmio_high_base, mmio_high_size); + memory_region_add_subregion(sysmem, mmio_high_base, + &s->pci.mmio_high_alias); + } + + for (i = 0; i < GPEX_NUM_IRQS; i++) { + qemu_irq irq = qemu_allocate_irq(xen_set_pci_intx_irq, s, i); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); + gpex_set_irq_num(GPEX_HOST(dev), i, intx_irq_base + i); + xen_set_pci_link_route(i, intx_irq_base + i); + } +} + static void xen_pvh_realize(DeviceState *dev, Error **errp) { XenPVHCommonState *s = XEN_PVH_COMMON(dev); @@ -152,6 +205,14 @@ static void xen_pvh_realize(DeviceState *dev, Error **errp) warn_report("tpm-base-addr is not provided. TPM will not be enabled"); } #endif + + if (s->cfg.ecam.size) { + xenpvh_gpex_init(s, sysmem, + s->cfg.ecam.base, s->cfg.ecam.size, + s->cfg.mmio.base, s->cfg.mmio.size, + s->cfg.mmio_high.base, s->cfg.mmio_high.size, + s->cfg.pci_intx_irq_base); + } } #define DEFINE_PROP_MEMMAP(n, f) \ @@ -165,10 +226,15 @@ static Property xen_pvh_properties[] = { DEFINE_PROP_MEMMAP("ram-high", ram_high), DEFINE_PROP_MEMMAP("virtio-mmio", virtio_mmio), DEFINE_PROP_MEMMAP("tpm", tpm), + DEFINE_PROP_MEMMAP("pci-ecam", ecam), + DEFINE_PROP_MEMMAP("pci-mmio", mmio), + DEFINE_PROP_MEMMAP("pci-mmio-high", mmio_high), DEFINE_PROP_UINT32("virtio-mmio-num", XenPVHCommonState, cfg.virtio_mmio_num, 0), DEFINE_PROP_UINT32("virtio-mmio-irq-base", XenPVHCommonState, cfg.virtio_mmio_irq_base, 0), + DEFINE_PROP_UINT32("pci-intx-irq-base", XenPVHCommonState, + cfg.pci_intx_irq_base, 0), DEFINE_PROP_END_OF_LIST() }; diff --git a/include/hw/xen/xen-pvh-common.h b/include/hw/xen/xen-pvh-common.h index e958b441fd..faacfca70e 100644 --- a/include/hw/xen/xen-pvh-common.h +++ b/include/hw/xen/xen-pvh-common.h @@ -29,17 +29,25 @@ typedef struct XenPVHCommonState { MemoryRegion high; } ram; + struct { + GPEXHost gpex; + MemoryRegion mmio_alias; + MemoryRegion mmio_high_alias; + } pci; + struct { uint64_t ram_size; uint32_t max_cpus; uint32_t virtio_mmio_num; uint32_t virtio_mmio_irq_base; + uint32_t pci_intx_irq_base; struct { uint64_t base; uint64_t size; } ram_low, ram_high, virtio_mmio, - tpm; + tpm, + ecam, mmio, mmio_high; } cfg; } XenPVHCommonState; #endif