[01/11] target/riscv: Add CLIC CSR mintstatus

Commit Message

Ian Brockbank Aug. 14, 2024, 8:27 a.m. UTC

From: Ian Brockbank <[e-mail]>

CSR mintstatus holds the active interrupt level for each supported
privilege mode. sintstatus, and user, uintstatus, provide restricted
views of mintstatus.

Signed-off-by: Ian Brockbank <[e-mail]>
Signed-off-by: LIU Zhiwei <[e-mail]>
---
 target/riscv/cpu.h      |  3 +++
 target/riscv/cpu_bits.h | 11 +++++++++++
 target/riscv/csr.c      | 31 +++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)

--
2.46.0.windows.1
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Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1619c3acb6..95303f50d3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -259,6 +259,7 @@  struct CPUArchState {
     bool software_seip;

     uint64_t miclaim;
+    uint64_t mintstatus; /* clic-spec */

     uint64_t mie;
     uint64_t mideleg;
@@ -461,6 +462,8 @@  struct CPUArchState {
     QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
     bool vstime_irq;

+    void *clic;       /* clic interrupt controller */
+
     hwaddr kernel_addr;
     hwaddr fdt_addr;

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 32b068f18a..2e65495b54 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -165,6 +165,7 @@ 
 #define CSR_MCAUSE          0x342
 #define CSR_MTVAL           0x343
 #define CSR_MIP             0x344
+#define CSR_MINTSTATUS      0xfb1 /* clic-spec-draft */

 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_MISELECT        0x350
@@ -206,6 +207,7 @@ 
 #define CSR_SCAUSE          0x142
 #define CSR_STVAL           0x143
 #define CSR_SIP             0x144
+#define CSR_SINTSTATUS      0xdb1 /* clic-spec-draft */

 /* Sstc supervisor CSRs */
 #define CSR_STIMECMP        0x14D
@@ -733,6 +735,15 @@  typedef enum RISCVException {
 #define SIP_SEIP                           MIP_SEIP
 #define SIP_LCOFIP                         MIP_LCOFIP

+/* mintstatus */
+#define MINTSTATUS_MIL                     0xff000000 /* mil[31:24] */
+#define MINTSTATUS_SIL                     0x0000ff00 /* sil[15:8] */
+#define MINTSTATUS_UIL                     0x000000ff /* uil[7:0] */
+
+/* sintstatus */
+#define SINTSTATUS_SIL                     0x0000ff00 /* sil[15:8] */
+#define SINTSTATUS_UIL                     0x000000ff /* uil[7:0] */
+
 /* MIE masks */
 #define MIE_SEIE                           (1 << IRQ_S_EXT)
 #define MIE_UEIE                           (1 << IRQ_U_EXT)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ea3560342c..f9ed7b9079 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -578,6 +578,16 @@  static RISCVException debug(CPURISCVState *env, int csrno)

     return RISCV_EXCP_ILLEGAL_INST;
 }
+
+static int clic(CPURISCVState *env, int csrno)
+{
+    if (env->clic) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
 #endif

 static RISCVException seed(CPURISCVState *env, int csrno)
@@ -2887,6 +2897,12 @@  static RISCVException rmw_mviph(CPURISCVState *env, int csrno,
     return ret;
 }

+static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    *val = env->mintstatus;
+    return RISCV_EXCP_NONE;
+}
+
 /* Supervisor Trap Setup */
 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
                                         Int128 *val)
@@ -3298,6 +3314,14 @@  static RISCVException rmw_siph(CPURISCVState *env, int csrno,
     return ret;
 }

+static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    /* sintstatus is a filtered view of mintstatus with the PRV_M removed */
+    target_ulong mask = SINTSTATUS_SIL | SINTSTATUS_UIL;
+    *val = env->mintstatus & mask;
+    return RISCV_EXCP_NONE;
+}
+
 /* Supervisor Protection and Translation */
 static RISCVException read_satp(CPURISCVState *env, int csrno,
                                 target_ulong *val)
@@ -5594,6 +5618,13 @@  riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
                              write_mhpmcounterh                         },
     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32,  read_hpmcounterh,
                              write_mhpmcounterh                         },
+
+    /* Machine Mode Core Level Interrupt Controller */
+    [CSR_MINTSTATUS]     = { "mintstatus", clic,  read_mintstatus       },
+
+    /* Supervisor Mode Core Level Interrupt Controller */
+    [CSR_SINTSTATUS]     = { "sintstatus", clic,  read_sintstatus       },
+
     [CSR_SCOUNTOVF]      = { "scountovf", sscofpmf,  read_scountovf,
                              .min_priv_ver = PRIV_VERSION_1_12_0 },