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[121.45.122.195]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d3ac7ca33dsm5988407a91.6.2024.08.16.10.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 10:10:23 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Jessica Clarke , Kyle Evans Subject: [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support Date: Sat, 17 Aug 2024 03:09:41 +1000 Message-Id: <20240816170949.238511-10-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240816170949.238511-1-itachis@FreeBSD.org> References: <20240816170949.238511-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Implemented functions for setting up and initializing threads in the RISC-V architecture. The 'target_thread_set_upcall' function sets up the stack pointer, program counter, and function argument for new threads. The 'target_thread_init' function initializes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans --- bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 bsd-user/riscv/target_arch_thread.h diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h new file mode 100644 index 0000000000..4596d3d51f --- /dev/null +++ b/bsd-user/riscv/target_arch_thread.h @@ -0,0 +1,47 @@ +/* + * RISC-V thread support + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_THREAD_H +#define TARGET_ARCH_THREAD_H + +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */ +static inline void target_thread_set_upcall(CPURISCVState *regs, + abi_ulong entry, abi_ulong arg, abi_ulong stack_base, + abi_ulong stack_size) +{ + abi_ulong sp; + + sp = (abi_ulong)(stack_base + stack_size) & ~(16 - 1); + + regs->gpr[xSP] = sp; + regs->pc = entry; + regs->gpr[xA0] = arg; +} + +/* Compare with exec_setregs() in riscv/riscv/machdep.c */ +static inline void target_thread_init(struct target_pt_regs *regs, + struct image_info *infop) +{ + regs->sepc = infop->entry; + regs->regs[xRA] = infop->entry; + regs->regs[xA0] = infop->start_stack; + regs->regs[xSP] = ROUND_DOWN(infop->start_stack,16); +} + +#endif /* TARGET_ARCH_THREAD_H */