From patchwork Mon Aug 19 16:02:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Brockbank X-Patchwork-Id: 13768578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7363C3DA4A for ; Mon, 19 Aug 2024 16:11:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sg4yZ-0006HA-3J; Mon, 19 Aug 2024 12:11:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sg4yW-00067Y-Pz; Mon, 19 Aug 2024 12:11:20 -0400 Received: from mx0a-001ae601.pphosted.com ([67.231.149.25] helo=mx0b-001ae601.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sg4yU-0007LC-SS; Mon, 19 Aug 2024 12:11:20 -0400 Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47JF6krt004009; Mon, 19 Aug 2024 11:09:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= PODMain02222019; bh=8+MWTdLJRX6DJEFL6fYcpdlaMSw1KJielO7I/ehLkJc=; b= OE9i1egf/LwV5pW4XCKNY2pE80nh13IueH8kBSh65HsIBbWBsvhYyyOyou0vleam FEIYoaTSAJpi4QhPLCHntWfPDBUu+wgG19iQkMqdmEQgMAIoS41F5UzdIyTzWdGF +zAwGezAqA6KODcg+CPqfEFNCI8CayNUn4cEcw8yHG84HD9f+RQXYorkN0Eax9ir kPPTcWJ6YkcYhipUnVoSSTlUUZqzdIETltZxUEN9G5/5yvIQXXyv1e8hMfVgVzV0 CNeF4wu15WjoEd7lv36j/JBYIknhnCPmc3t8sMCS4I54vO7+qvBZUTnDPbkplNXy bK7PUhjhvTcM4mN9m+H++A== Received: from ausex02.ad.cirrus.com ([141.131.3.21]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 412s8x1x73-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Aug 2024 11:08:56 -0500 (CDT) Received: from ausex01.ad.cirrus.com (141.131.37.95) by ausex02.ad.cirrus.com (141.131.37.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 19 Aug 2024 11:08:55 -0500 Received: from EDIN7BQBTG3.ad.cirrus.com (141.131.38.212) by anon-ausex01.ad.cirrus.com (141.131.37.95) with Microsoft SMTP Server id 15.2.1544.9 via Frontend Transport; Mon, 19 Aug 2024 11:08:53 -0500 From: Ian Brockbank To: , CC: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ian Brockbank , LIU Zhiwei Subject: [PATCH 02/11 v2] target/riscv: Update CSR xintthresh in CLIC mode Date: Mon, 19 Aug 2024 17:02:12 +0100 Message-ID: <20240819160742.27586-5-Ian.Brockbank@cirrus.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240819160742.27586-1-Ian.Brockbank@cirrus.com> References: <20240819160742.27586-1-Ian.Brockbank@cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: g0sAVv0QH9pMyTkkLd_5Pz2MOhwHayzf X-Proofpoint-GUID: g0sAVv0QH9pMyTkkLd_5Pz2MOhwHayzf X-Proofpoint-Spam-Reason: safe Received-SPF: pass client-ip=67.231.149.25; envelope-from=prvs=5961d01319=ian.brockbank@cirrus.com; helo=mx0b-001ae601.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ian Brockbank The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: Ian Brockbank Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+) -- 2.46.0.windows.1 This message and any attachments may contain privileged and confidential information that is intended solely for the person(s) to whom it is addressed. If you are not an intended recipient you must not: read; copy; distribute; discuss; take any action in or make any reliance upon the contents of this message; nor open or read any attachment. If you have received this message in error, please notify us as soon as possible on the following telephone number and destroy this message including any attachments. Thank you. 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Tel: +44 (0)131 272 7000. www.cirrus.com diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 95303f50d3..9b5f36ad0a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -260,6 +260,7 @@ struct CPUArchState { uint64_t miclaim; uint64_t mintstatus; /* clic-spec */ + target_ulong mintthresh; /* clic-spec */ uint64_t mie; uint64_t mideleg; @@ -283,6 +284,7 @@ struct CPUArchState { target_ulong stvec; target_ulong sepc; target_ulong scause; + target_ulong sintthresh; /* clic-spec */ target_ulong mtvec; target_ulong mepc; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 2e65495b54..ad45402370 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -166,6 +166,7 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 #define CSR_MINTSTATUS 0xfb1 /* clic-spec-draft */ +#define CSR_MINTTHRESH 0x347 /* clic-spec-draft */ /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_MISELECT 0x350 @@ -208,6 +209,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SINTSTATUS 0xdb1 /* clic-spec-draft */ +#define CSR_SINTTHRESH 0x147 /* clic-spec-draft */ /* Sstc supervisor CSRs */ #define CSR_STIMECMP 0x14D diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9ed7b9079..9c824c0d8f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2903,6 +2903,18 @@ static int read_mintstatus(CPURISCVState *env, int csrno, target_ulong *val) return RISCV_EXCP_NONE; } +static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mintthresh; + return 0; +} + +static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mintthresh = val; + return 0; +} + /* Supervisor Trap Setup */ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, Int128 *val) @@ -3322,6 +3334,18 @@ static int read_sintstatus(CPURISCVState *env, int csrno, target_ulong *val) return RISCV_EXCP_NONE; } +static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->sintthresh; + return 0; +} + +static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong val) +{ + env->sintthresh = val; + return 0; +} + /* Supervisor Protection and Translation */ static RISCVException read_satp(CPURISCVState *env, int csrno, target_ulong *val) @@ -5621,9 +5645,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Machine Mode Core Level Interrupt Controller */ [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus }, + [CSR_MINTTHRESH] = { "mintthresh", clic, read_mintthresh, + write_mintthresh }, /* Supervisor Mode Core Level Interrupt Controller */ [CSR_SINTSTATUS] = { "sintstatus", clic, read_sintstatus }, + [CSR_SINTTHRESH] = { "sintthresh", clic, read_sintthresh, + write_sintthresh }, [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf, .min_priv_ver = PRIV_VERSION_1_12_0 },