From patchwork Sat Aug 24 04:56:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13776317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12653C52D6F for ; Sat, 24 Aug 2024 04:59:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1shipm-0006eO-0y; Sat, 24 Aug 2024 00:57:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1shipk-0006Zh-Ma for qemu-devel@nongnu.org; Sat, 24 Aug 2024 00:57:04 -0400 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1shipj-0002Fe-0t for qemu-devel@nongnu.org; Sat, 24 Aug 2024 00:57:04 -0400 Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-70e00cb1ee7so1955806a34.1 for ; Fri, 23 Aug 2024 21:57:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724475422; x=1725080222; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=cKdP30AxvTK8EfFWnZVNkOWd5iUyz4STMPomUTSEw5eKFn5+sGzIyO0/x+YEIW828v JrEdoiFB4zGz6dV6FxmEAfzLCjrY/7rNejWQ+6cF8B9Np2NvpkgUMLR/1L7h22PY6c+I LOVe6y0GaaVf/hhoMMg8eFh63dt0a/01fMuU3uMsLyo8h69QZH/apkw2NAp7bDlyiRPC oyiGylOF9VvvTH/Ak0EVhCrBV1HCwdLb6VL3Wzc5q5xVD/9UjeArLJTjqIJtjNBOpJAO VBfQ90lV5rMvdjhGfATNmCLOq/K3O7WT92Hr2iBZy0wFUMxTZg3FkBh2umrZ13OdPQw6 AQwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724475422; x=1725080222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=Wwh9F0mvSeZlkGF/OwbPkW+SNDgBwDfncIjBJa9nM68KI3WrRywzLoB9gBR3gnlQ5I +tKupw3Gisx0YZorJ1GYEUhqGyHmJxP6+AVYxU+qn1gkeV25SarQOoVB/+aCiZ12KCjF pylHEQldA7KIii26L48fFq29e4uwiszhNby+1h++2f1UcJlvf4E52Uf5vvXTuIjlwLWY dHnoaCe3pDN5eebAzHEmJP4iDAcKQX+57uCFtp5OmANK4/vSy6kfKEOdyDpkE8X6Hl11 tHZaErimANmHRmQHSTmTn5vqyhnCNZ0wVSDE1B57YxmFbeDL2xOXUTgHaHtPwLgJaLx5 Z4SQ== X-Gm-Message-State: AOJu0Yy83zctNOLp2mGLAIB6QVFW1zkkWE6ekJhSDSCg+2fnUwCalwgf DgieZm4LiQg9JrjTgWF6RaPNOq3pYoBVuFlWNL9gq2/5ad28QQ+x8DnI+WzcpSw= X-Google-Smtp-Source: AGHT+IEqZcgyHVjVo+1w4UmF1l00liOLIPcRToP9E2K9wxf3BOYPMJ96AizawETjTR22XtxS6JADWw== X-Received: by 2002:a05:6808:22a5:b0:3da:b335:538e with SMTP id 5614622812f47-3de2a84071amr5193978b6e.8.1724475421599; Fri, 23 Aug 2024 21:57:01 -0700 (PDT) Received: from localhost.localdomain ([220.253.126.131]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7143422ecedsm3805934b3a.25.2024.08.23.21.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Aug 2024 21:57:01 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Mark Corbin , Ajeet Singh , Kyle Evans , Richard Henderson Subject: [PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Date: Sat, 24 Aug 2024 14:56:23 +1000 Message-Id: <20240824045635.8978-6-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240824045635.8978-1-itachis@FreeBSD.org> References: <20240824045635.8978-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=itachis6234@gmail.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h new file mode 100644 index 0000000000..4eb915e61e --- /dev/null +++ b/bsd-user/riscv/target_arch_elf.h @@ -0,0 +1,42 @@ +/* + * RISC-V ELF definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#define elf_check_arch(x) ((x) == EM_RISCV) +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 +#define ELF_CLASS ELFCLASS64 + +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_RISCV + +#define ELF_HWCAP get_elf_hwcap() +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + + return cpu->env.misa_ext_mask; +} + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* TARGET_ARCH_ELF_H */