| Message ID | 20240827035807.3326293-1-maobibo@loongson.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/loongarch: Add compatible support about VM reboot | expand |
在 2024/8/27 上午11:58, Bibo Mao 写道: > With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only > if its value is equal to zero for boot cpu, it causes reboot issue. Since > CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it. > > Add workaround to clear CSR registers relative with TLB in function > loongarch_cpu_reset_hold(), so that VM can reboot with edk2-stable202408 > UEFI bios. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > target/loongarch/cpu.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > Reviewed-by: Song Gao <gaosong@loongson.cn> Thanks Song Gao > diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c > index 5e85b9dbef..2f4d635d03 100644 > --- a/target/loongarch/cpu.c > +++ b/target/loongarch/cpu.c > @@ -549,6 +549,20 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) > env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); > env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); > env->CSR_TID = cs->cpu_index; > + /* > + * Workaround for edk2-stable202408, CSR PGD register is set only if > + * its value is equal to zero for boot cpu, it causes reboot issue. > + * > + * Here clear CSR registers relative with TLB. > + */ > + env->CSR_PGDH = 0; > + env->CSR_PGDL = 0; > + env->CSR_PWCL = 0; > + env->CSR_PWCH = 0; > + env->CSR_STLBPS = 0; > + env->CSR_EENTRY = 0; > + env->CSR_TLBRENTRY = 0; > + env->CSR_MERRENTRY = 0; > > for (n = 0; n < 4; n++) { > env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); > > base-commit: f259e4cb8a8b4ef5463326fc214a7d8d7703d5de >
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 5e85b9dbef..2f4d635d03 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -549,6 +549,20 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type) env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0); env->CSR_TID = cs->cpu_index; + /* + * Workaround for edk2-stable202408, CSR PGD register is set only if + * its value is equal to zero for boot cpu, it causes reboot issue. + * + * Here clear CSR registers relative with TLB. + */ + env->CSR_PGDH = 0; + env->CSR_PGDL = 0; + env->CSR_PWCL = 0; + env->CSR_PWCH = 0; + env->CSR_STLBPS = 0; + env->CSR_EENTRY = 0; + env->CSR_TLBRENTRY = 0; + env->CSR_MERRENTRY = 0; for (n = 0; n < 4; n++) { env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only if its value is equal to zero for boot cpu, it causes reboot issue. Since CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it. Add workaround to clear CSR registers relative with TLB in function loongarch_cpu_reset_hold(), so that VM can reboot with edk2-stable202408 UEFI bios. Signed-off-by: Bibo Mao <maobibo@loongson.cn> --- target/loongarch/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) base-commit: f259e4cb8a8b4ef5463326fc214a7d8d7703d5de