From patchwork Wed Aug 28 09:52:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13781016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6815FC54E71 for ; Wed, 28 Aug 2024 09:54:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sjFMW-000260-4c; Wed, 28 Aug 2024 05:53:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sjFMT-0001zc-VN for qemu-devel@nongnu.org; Wed, 28 Aug 2024 05:53:10 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sjFMS-0001od-8r for qemu-devel@nongnu.org; Wed, 28 Aug 2024 05:53:09 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-7142e002aceso5313711b3a.2 for ; Wed, 28 Aug 2024 02:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1724838787; x=1725443587; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=d+LpRhdoODUr6dH0yRiIbYS8+U9RKvwf2A2NaNgftxSE6CXDf3jym46GZyJedfjF08 vx+wksINRpT4NHU4cjMTJkjr7+u4fdTuDxJBW492tqb6BLcDwkZMXalDgRDmRU1XaAet uD4drloJ2Zsh3ooYCkaSp6yCGZuyAj/dTs0QyHJaVk97DuqZ9PHwhouc2vpek5tbPKXQ Ijg4vK0ZexkwViGAXVXDqF3yYnjNLM9SJKWhGhJ//lwqmdjw76WuOvs6VVaEcF+j7WlX jBX/xwwvs/sTj8X7EMyoDaZIBkhzUDYlzor+swMVp/nZG4EGPcta1vP08Esj4yRg2JPU MLrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724838787; x=1725443587; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=Ut2LxMqoSZzw6F6ERJtF0uOWkjc82MziHXVK++JzpS3puHzARwRcW9s+GOplN1ZQnT efLOIlEXuFTArs+30KyWwKgLH0lM/+mdca9VuQ7eN5n6Hp4YiF5KRfqEPedEY+NAHtkD mg7gWwG3MRX9DtiexIYdPNTTTBHuTOls35cUPtajiFRCzXgf7UZ2SSViPVt1fnUaDA/g z/SaEFxKgooe/tnnGEIpyF/KCdrqWnsAtqiD+q9W2CCpyRDwGARX2lc5Ndh2OfJa4Ris CuenbRVridD4PBmbqMHV4xef3ZIJf6hAvrNlYG50PS4vvslcIkwTkl13DVUFUND3r7H9 sGdg== X-Gm-Message-State: AOJu0YyBc2kSucGU2CRRu7+1jUUhtltqM/oDkSuz/IxwjCv2qySoFWCm jhIDNS1nB/buG28u5BYio9i98WYnLTa6baxNaFm/CfnDynsvp0rcex40e/hP X-Google-Smtp-Source: AGHT+IEskS5wugh01RHkDYqs6hkB0X0lB4wI8izTQKz/6rOfKnUIixQVtVDCmaXNk63iCJHipMLqsA== X-Received: by 2002:a05:6a00:194d:b0:706:6c38:31f3 with SMTP id d2e1a72fcca58-715d10c19fdmr1547352b3a.8.1724838786539; Wed, 28 Aug 2024 02:53:06 -0700 (PDT) Received: from localhost.localdomain ([220.253.126.131]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7143430f6e7sm9787508b3a.160.2024.08.28.02.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Aug 2024 02:53:06 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Mark Corbin , Warner Losh , Ajeet Singh , Kyle Evans , Richard Henderson Subject: [PATCH v4 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Date: Wed, 28 Aug 2024 19:52:31 +1000 Message-Id: <20240828095243.90491-6-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828095243.90491-1-itachis@FreeBSD.org> References: <20240828095243.90491-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=itachis6234@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h new file mode 100644 index 0000000000..4eb915e61e --- /dev/null +++ b/bsd-user/riscv/target_arch_elf.h @@ -0,0 +1,42 @@ +/* + * RISC-V ELF definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#define elf_check_arch(x) ((x) == EM_RISCV) +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 +#define ELF_CLASS ELFCLASS64 + +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_RISCV + +#define ELF_HWCAP get_elf_hwcap() +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + + return cpu->env.misa_ext_mask; +} + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* TARGET_ARCH_ELF_H */