@@ -474,6 +474,90 @@ static inline const char *nvme_io_opc_str(uint8_t opc)
}
}
+static inline NvmeResvType block_pr_type_to_nvme(BlockPrType type)
+{
+ switch (type) {
+ case BLK_PR_WRITE_EXCLUSIVE:
+ return NVME_RESV_WRITE_EXCLUSIVE;
+ case BLK_PR_EXCLUSIVE_ACCESS:
+ return NVME_RESV_EXCLUSIVE_ACCESS;
+ case BLK_PR_WRITE_EXCLUSIVE_REGS_ONLY:
+ return NVME_RESV_WRITE_EXCLUSIVE_REGS_ONLY;
+ case BLK_PR_EXCLUSIVE_ACCESS_REGS_ONLY:
+ return NVME_RESV_EXCLUSIVE_ACCESS_REGS_ONLY;
+ case BLK_PR_WRITE_EXCLUSIVE_ALL_REGS:
+ return NVME_RESV_WRITE_EXCLUSIVE_ALL_REGS;
+ case BLK_PR_EXCLUSIVE_ACCESS_ALL_REGS:
+ return NVME_RESV_EXCLUSIVE_ACCESS_ALL_REGS;
+ }
+
+ return 0;
+}
+
+static inline BlockPrType nvme_pr_type_to_block(NvmeResvType type)
+{
+ switch (type) {
+ case NVME_RESV_WRITE_EXCLUSIVE:
+ return BLK_PR_WRITE_EXCLUSIVE;
+ case NVME_RESV_EXCLUSIVE_ACCESS:
+ return BLK_PR_EXCLUSIVE_ACCESS;
+ case NVME_RESV_WRITE_EXCLUSIVE_REGS_ONLY:
+ return BLK_PR_WRITE_EXCLUSIVE_REGS_ONLY;
+ case NVME_RESV_EXCLUSIVE_ACCESS_REGS_ONLY:
+ return BLK_PR_EXCLUSIVE_ACCESS_REGS_ONLY;
+ case NVME_RESV_WRITE_EXCLUSIVE_ALL_REGS:
+ return BLK_PR_WRITE_EXCLUSIVE_ALL_REGS;
+ case NVME_RESV_EXCLUSIVE_ACCESS_ALL_REGS:
+ return BLK_PR_EXCLUSIVE_ACCESS_ALL_REGS;
+ }
+
+ return 0;
+}
+
+static inline uint8_t nvme_pr_cap_to_block(uint16_t nvme_pr_cap)
+{
+ uint8_t res = 0;
+
+ res |= (nvme_pr_cap & NVME_PR_CAP_PTPL) ?
+ NVME_PR_CAP_PTPL : 0;
+ res |= (nvme_pr_cap & NVME_PR_CAP_WR_EX) ?
+ BLK_PR_CAP_WR_EX : 0;
+ res |= (nvme_pr_cap & NVME_PR_CAP_EX_AC) ?
+ BLK_PR_CAP_EX_AC : 0;
+ res |= (nvme_pr_cap & NVME_PR_CAP_WR_EX_RO) ?
+ BLK_PR_CAP_WR_EX_RO : 0;
+ res |= (nvme_pr_cap & NVME_PR_CAP_EX_AC_RO) ?
+ BLK_PR_CAP_EX_AC_RO : 0;
+ res |= (nvme_pr_cap & NVME_PR_CAP_WR_EX_AR) ?
+ BLK_PR_CAP_WR_EX_AR : 0;
+ res |= (nvme_pr_cap & NVME_PR_CAP_EX_AC_AR) ?
+ BLK_PR_CAP_EX_AC_AR : 0;
+
+ return res;
+}
+
+static inline uint8_t block_pr_cap_to_nvme(uint8_t block_pr_cap)
+{
+ uint16_t res = 0;
+
+ res |= (block_pr_cap & BLK_PR_CAP_PTPL) ?
+ NVME_PR_CAP_PTPL : 0;
+ res |= (block_pr_cap & BLK_PR_CAP_WR_EX) ?
+ NVME_PR_CAP_WR_EX : 0;
+ res |= (block_pr_cap & BLK_PR_CAP_EX_AC) ?
+ NVME_PR_CAP_EX_AC : 0;
+ res |= (block_pr_cap & BLK_PR_CAP_WR_EX_RO) ?
+ NVME_PR_CAP_WR_EX_RO : 0;
+ res |= (block_pr_cap & BLK_PR_CAP_EX_AC_RO) ?
+ NVME_PR_CAP_EX_AC_RO : 0;
+ res |= (block_pr_cap & BLK_PR_CAP_WR_EX_AR) ?
+ NVME_PR_CAP_WR_EX_AR : 0;
+ res |= (block_pr_cap & BLK_PR_CAP_EX_AC_AR) ?
+ NVME_PR_CAP_EX_AC_AR : 0;
+
+ return res;
+}
+
typedef struct NvmeSQueue {
struct NvmeCtrl *ctrl;
uint16_t sqid;