| Message ID | 20240902071358.1061693-5-tommy.wu@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add Smrnmi support. | expand |
On Mon, Sep 2, 2024 at 5:14 PM Tommy Wu <tommy.wu@sifive.com> wrote: > > This patch adds a new instruction `mnret`. `mnret` is an M-mode-only > instruction that uses the values in `mnepc` and `mnstatus` to return to the > program counter, privilege mode, and virtualization mode of the > interrupted context. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Signed-off-by: Tommy Wu <tommy.wu@sifive.com> > --- > target/riscv/helper.h | 1 + > target/riscv/insn32.decode | 3 ++ > .../riscv/insn_trans/trans_privileged.c.inc | 12 +++++ > target/riscv/op_helper.c | 49 +++++++++++++++++-- > 4 files changed, 60 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 451261ce5a..16ea240d26 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) > #ifndef CONFIG_USER_ONLY > DEF_HELPER_1(sret, tl, env) > DEF_HELPER_1(mret, tl, env) > +DEF_HELPER_1(mnret, tl, env) > DEF_HELPER_1(wfi, void, env) > DEF_HELPER_1(wrs_nto, void, env) > DEF_HELPER_1(tlb_flush, void, env) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index c45b8fa1d8..d320631e8c 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -121,6 +121,9 @@ wfi 0001000 00101 00000 000 00000 1110011 > sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma > sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm > > +# *** NMI *** > +mnret 0111000 00010 00000 000 00000 1110011 > + > # *** RV32I Base Instruction Set *** > lui .................... ..... 0110111 @u > auipc .................... ..... 0010111 @u > diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc > index bc5263a4e0..06bc20dda4 100644 > --- a/target/riscv/insn_trans/trans_privileged.c.inc > +++ b/target/riscv/insn_trans/trans_privileged.c.inc > @@ -106,6 +106,18 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) > #endif > } > > +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) > +{ > +#ifndef CONFIG_USER_ONLY You will want to include a REQUIRE_SMRNMI(ctx) function here. Have a look at REQUIRE_A_OR_ZAAMO(ctx) for an example of what it should look like. > + gen_helper_mnret(cpu_pc, tcg_env); > + tcg_gen_exit_tb(NULL, 0); /* no chaining */ > + ctx->base.is_jmp = DISAS_NORETURN; This will need to be rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next We will want to call decode_save_opc() and the other functions here > + return true; > +#else > + return false; > +#endif > +} > + > static bool trans_wfi(DisasContext *ctx, arg_wfi *a) > { > #ifndef CONFIG_USER_ONLY > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 25a5263573..6895c7596b 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -312,24 +312,30 @@ target_ulong helper_sret(CPURISCVState *env) > return retpc; > } > > -target_ulong helper_mret(CPURISCVState *env) > +static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, > + target_ulong prev_priv) > { > if (!(env->priv >= PRV_M)) { > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > } > > - target_ulong retpc = env->mepc; > if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { > riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); > } > > - uint64_t mstatus = env->mstatus; > - target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); > - > if (riscv_cpu_cfg(env)->pmp && > !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { > riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); > } > +} > + > +target_ulong helper_mret(CPURISCVState *env) > +{ > + target_ulong retpc = env->mepc; > + uint64_t mstatus = env->mstatus; > + target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); > + > + check_ret_from_m_mode(env, retpc, prev_priv); > > target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) && > (prev_priv != PRV_M); > @@ -353,6 +359,39 @@ target_ulong helper_mret(CPURISCVState *env) > return retpc; > } > > +target_ulong helper_mnret(CPURISCVState *env) > +{ > + if (!riscv_cpu_cfg(env)->ext_smrnmi) { > + /* RNMI feature is not presented. */ > + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + } > + > + target_ulong retpc = env->mnepc; > + target_ulong prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP); Variables should be declared before any other code in a function. With a REQUIRE_SMRNMI() you can drop the check above anyway. Alistair > + > + check_ret_from_m_mode(env, retpc, prev_priv); > + > + target_ulong prev_virt = get_field(env->mnstatus, MNSTATUS_MNPV) && > + (prev_priv != PRV_M); > + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, true); > + > + /* > + * If MNRET changes the privilege mode to a mode > + * less privileged than M, it also sets mstatus.MPRV to 0. > + */ > + if (prev_priv < PRV_M) { > + env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); > + } > + > + if (riscv_has_ext(env, RVH) && prev_virt) { > + riscv_cpu_swap_hypervisor_regs(env); > + } > + > + riscv_cpu_set_mode(env, prev_priv, prev_virt); > + > + return retpc; > +} > + > void helper_wfi(CPURISCVState *env) > { > CPUState *cs = env_cpu(env); > -- > 2.39.3 >
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 451261ce5a..16ea240d26 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c45b8fa1d8..d320631e8c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -121,6 +121,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index bc5263a4e0..06bc20dda4 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -106,6 +106,18 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_mnret(cpu_pc, tcg_env); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 25a5263573..6895c7596b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -312,24 +312,30 @@ target_ulong helper_sret(CPURISCVState *env) return retpc; } -target_ulong helper_mret(CPURISCVState *env) +static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, + target_ulong prev_priv) { if (!(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } - target_ulong retpc = env->mepc; if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } - uint64_t mstatus = env->mstatus; - target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); - if (riscv_cpu_cfg(env)->pmp && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } +} + +target_ulong helper_mret(CPURISCVState *env) +{ + target_ulong retpc = env->mepc; + uint64_t mstatus = env->mstatus; + target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); + + check_ret_from_m_mode(env, retpc, prev_priv); target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) && (prev_priv != PRV_M); @@ -353,6 +359,39 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } +target_ulong helper_mnret(CPURISCVState *env) +{ + if (!riscv_cpu_cfg(env)->ext_smrnmi) { + /* RNMI feature is not presented. */ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + target_ulong retpc = env->mnepc; + target_ulong prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP); + + check_ret_from_m_mode(env, retpc, prev_priv); + + target_ulong prev_virt = get_field(env->mnstatus, MNSTATUS_MNPV) && + (prev_priv != PRV_M); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, true); + + /* + * If MNRET changes the privilege mode to a mode + * less privileged than M, it also sets mstatus.MPRV to 0. + */ + if (prev_priv < PRV_M) { + env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); + } + + if (riscv_has_ext(env, RVH) && prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_mode(env, prev_priv, prev_virt); + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs = env_cpu(env);