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Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Herv=C3=A9_Poussin?= =?utf-8?q?eau?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , qemu-arm@nongnu.org, Guenter Roeck Subject: [RFC PATCH 7/8] aspeed: Add uhci support for ast2600 Date: Fri, 6 Sep 2024 05:25:41 -0700 Message-ID: <20240906122542.3808997-8-linux@roeck-us.net> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240906122542.3808997-1-linux@roeck-us.net> References: <20240906122542.3808997-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=groeck7@gmail.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Enable UHCO support for the ast2600 SoC. With this patch, the UHCI port is successfully instantiated on the rainier-bmc and ast2600-evb machines. Signed-off-by: Guenter Roeck Reviewed-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c | 13 +++++++++++++ include/hw/arm/aspeed_soc.h | 3 +++ 2 files changed, 16 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index be3eb70cdd..cd7e4ae6c9 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -33,6 +33,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_DEV_SPI2] = 0x1E631000, [ASPEED_DEV_EHCI1] = 0x1E6A1000, [ASPEED_DEV_EHCI2] = 0x1E6A3000, + [ASPEED_DEV_UHCI] = 0x1E6B0000, [ASPEED_DEV_MII1] = 0x1E650000, [ASPEED_DEV_MII2] = 0x1E650008, [ASPEED_DEV_MII3] = 0x1E650010, @@ -110,6 +111,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_DEV_SDHCI] = 43, [ASPEED_DEV_EHCI1] = 5, [ASPEED_DEV_EHCI2] = 9, + [ASPEED_DEV_UHCI] = 10, [ASPEED_DEV_EMMC] = 15, [ASPEED_DEV_GPIO] = 40, [ASPEED_DEV_GPIO_1_8V] = 11, @@ -206,6 +208,8 @@ static void aspeed_soc_ast2600_init(Object *obj) TYPE_PLATFORM_EHCI); } + object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); object_initialize_child(obj, "sdmc", &s->sdmc, typename); object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), @@ -481,6 +485,15 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); } + /* UHCI */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, + sc->memmap[ASPEED_DEV_UHCI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); + /* SDMC - SDRAM Memory Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { return; diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 624d489e0d..b54849db72 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -34,6 +34,7 @@ #include "hw/gpio/aspeed_gpio.h" #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" +#include "hw/usb/hcd-uhci-sysbus.h" #include "qom/object.h" #include "hw/misc/aspeed_lpc.h" #include "hw/misc/unimp.h" @@ -72,6 +73,7 @@ struct AspeedSoCState { AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; EHCISysBusState ehci[ASPEED_EHCIS_NUM]; + ASPEEDUHCIState uhci; AspeedSBCState sbc; AspeedSLIState sli; AspeedSLIState sliio; @@ -193,6 +195,7 @@ enum { ASPEED_DEV_SPI2, ASPEED_DEV_EHCI1, ASPEED_DEV_EHCI2, + ASPEED_DEV_UHCI, ASPEED_DEV_VIC, ASPEED_DEV_INTC, ASPEED_DEV_SDMC,