| Message ID | 20240925151330.50215-2-paolo.savini@embecosm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode. | expand |
Paolo, Usually we amend the existing patch with a new version instead of sending a new patch to amend a previous patch that got comments. I suggest you merge this change with your first patch here: https://patchew.org/QEMU/20240717153040.11073-1-paolo.savini@embecosm.com/20240717153040.11073-2-paolo.savini@embecosm.com/#aff5f930-d291-4ff5-8f24-53291059d59a@linaro.org Set it as v2 and re-send. Thanks, Daniel On 9/25/24 12:13 PM, Paolo Savini wrote: > The simplified emulation of vector loads and stores that bypasses the memory > probing in the vext_ldst_us helper function seem to benefit only the user mode. > We therefore limit this approach to the user mode configuration. > > Signed-off-by: Paolo Savini <paolo.savini@embecosm.com> > --- > target/riscv/vector_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 9026661573..08f71abc22 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -648,6 +648,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, > > VSTART_CHECK_EARLY_EXIT(env); > > +#ifdef CONFIG_USER_ONLY > /* For data sizes <= 64 bits and for LMUL=1 with VLEN=128 bits we get a > * better performance by doing a simple simulation of the load/store > * without the overhead of prodding the host RAM */ > @@ -692,7 +693,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, > vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems); > return; > } > - > +#endif > > vext_cont_ldst_elements(&info, base, env->vreg, env->vstart, evl, desc, > log2_esz, false);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9026661573..08f71abc22 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -648,6 +648,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, VSTART_CHECK_EARLY_EXIT(env); +#ifdef CONFIG_USER_ONLY /* For data sizes <= 64 bits and for LMUL=1 with VLEN=128 bits we get a * better performance by doing a simple simulation of the load/store * without the overhead of prodding the host RAM */ @@ -692,7 +693,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems); return; } - +#endif vext_cont_ldst_elements(&info, base, env->vreg, env->vstart, evl, desc, log2_esz, false);
The simplified emulation of vector loads and stores that bypasses the memory probing in the vext_ldst_us helper function seem to benefit only the user mode. We therefore limit this approach to the user mode configuration. Signed-off-by: Paolo Savini <paolo.savini@embecosm.com> --- target/riscv/vector_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)