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[88.28.18.183]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a362bcsm144722025e9.36.2024.09.30.02.12.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 02:12:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson Subject: [PATCH 08/12] target/mips: Expose MIPSCPU::is_big_endian property Date: Mon, 30 Sep 2024 11:10:57 +0200 Message-ID: <20240930091101.40591-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930091101.40591-1-philmd@linaro.org> References: <20240930091101.40591-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a175a..070e11fe0d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,6 +1209,9 @@ struct ArchCPU { Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ + + /* Properties */ + bool is_big_endian; }; /** diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1900..982f5bb4e2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; + env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, + CP0C0_BE, 1, cpu->is_big_endian); #if TARGET_BIG_ENDIAN env->CP0_Config0 |= (1 << CP0C0_BE); #endif @@ -541,6 +542,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = { }; #endif +static Property mips_cpu_properties[] = { + DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -571,6 +577,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) DeviceClass *dc = DEVICE_CLASS(c); ResettableClass *rc = RESETTABLE_CLASS(c); + device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,