| Message ID | 20240930092631.2997543-8-zhenzhong.duan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | intel_iommu: Enable stage-1 translation for emulated device | expand |
On 2024/9/30 17:26, Zhenzhong Duan wrote: > From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> > > First stage translation must fail if the address to translate is > not canonical. > > Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com> > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > Acked-by: Jason Wang <jasowang@redhat.com> > --- > hw/i386/intel_iommu_internal.h | 2 ++ > hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++ > 2 files changed, 25 insertions(+) Reviewed-by: Yi Liu <yi.l.liu@intel.com> > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 38bf0c7a06..57c50648ce 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -320,6 +320,8 @@ typedef enum VTDFaultReason { > VTD_FR_PASID_ENTRY_P = 0x59, > VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */ > > + VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/ > + > /* Output address in the interrupt address range for scalable mode */ > VTD_FR_SM_INTERRUPT_ADDR = 0x87, > VTD_FR_MAX, /* Guard */ > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 56d5933e93..ec0596c2b2 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -1821,6 +1821,7 @@ static const bool vtd_qualified_faults[] = { > [VTD_FR_PASID_ENTRY_P] = true, > [VTD_FR_PASID_TABLE_ENTRY_INV] = true, > [VTD_FR_SM_INTERRUPT_ADDR] = true, > + [VTD_FR_FS_NON_CANONICAL] = true, > [VTD_FR_MAX] = false, > }; > > @@ -1924,6 +1925,22 @@ static inline bool vtd_flpte_present(uint64_t flpte) > return !!(flpte & VTD_FL_P); > } > > +/* Return true if IOVA is canonical, otherwise false. */ > +static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova, > + VTDContextEntry *ce, uint32_t pasid) > +{ > + uint64_t iova_limit = vtd_iova_limit(s, ce, s->aw_bits, pasid); > + uint64_t upper_bits_mask = ~(iova_limit - 1); > + uint64_t upper_bits = iova & upper_bits_mask; > + bool msb = ((iova & (iova_limit >> 1)) != 0); > + > + if (msb) { > + return upper_bits == upper_bits_mask; > + } else { > + return !upper_bits; > + } > +} > + > /* > * Given the @iova, get relevant @flptep. @flpte_level will be the last level > * of the translation, can be used for deciding the size of large page. > @@ -1939,6 +1956,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce, > uint32_t offset; > uint64_t flpte; > > + if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { > + error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 "," > + "pasid=0x%" PRIx32 ")", __func__, iova, pasid); > + return -VTD_FR_FS_NON_CANONICAL; > + } > + > while (true) { > offset = vtd_iova_level_offset(iova, level); > flpte = vtd_get_pte(addr, offset);
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 38bf0c7a06..57c50648ce 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -320,6 +320,8 @@ typedef enum VTDFaultReason { VTD_FR_PASID_ENTRY_P = 0x59, VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */ + VTD_FR_FS_NON_CANONICAL = 0x80, /* SNG.1 : Address for FS not canonical.*/ + /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR = 0x87, VTD_FR_MAX, /* Guard */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 56d5933e93..ec0596c2b2 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1821,6 +1821,7 @@ static const bool vtd_qualified_faults[] = { [VTD_FR_PASID_ENTRY_P] = true, [VTD_FR_PASID_TABLE_ENTRY_INV] = true, [VTD_FR_SM_INTERRUPT_ADDR] = true, + [VTD_FR_FS_NON_CANONICAL] = true, [VTD_FR_MAX] = false, }; @@ -1924,6 +1925,22 @@ static inline bool vtd_flpte_present(uint64_t flpte) return !!(flpte & VTD_FL_P); } +/* Return true if IOVA is canonical, otherwise false. */ +static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova, + VTDContextEntry *ce, uint32_t pasid) +{ + uint64_t iova_limit = vtd_iova_limit(s, ce, s->aw_bits, pasid); + uint64_t upper_bits_mask = ~(iova_limit - 1); + uint64_t upper_bits = iova & upper_bits_mask; + bool msb = ((iova & (iova_limit >> 1)) != 0); + + if (msb) { + return upper_bits == upper_bits_mask; + } else { + return !upper_bits; + } +} + /* * Given the @iova, get relevant @flptep. @flpte_level will be the last level * of the translation, can be used for deciding the size of large page. @@ -1939,6 +1956,12 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce, uint32_t offset; uint64_t flpte; + if (!vtd_iova_fl_check_canonical(s, iova, ce, pasid)) { + error_report_once("%s: detected non canonical IOVA (iova=0x%" PRIx64 "," + "pasid=0x%" PRIx32 ")", __func__, iova, pasid); + return -VTD_FR_FS_NON_CANONICAL; + } + while (true) { offset = vtd_iova_level_offset(iova, level); flpte = vtd_get_pte(addr, offset);