| Message ID | 20241002055048.556083-1-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 2 Oct 2024 at 06:51, Alistair Francis <alistair23@gmail.com> wrote: > > The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855: > > Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into staging (2024-10-01 11:34:07 +0100) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241002 > > for you to fetch changes up to 74b493244d0624afed22606e76fc7fca62777401: > > bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files (2024-10-02 15:11:52 +1000) > > ---------------------------------------------------------------- > RISC-V PR for 9.2 > > * Add a property to set vl to ceil(AVL/2) > * Enable numamem testing for RISC-V > * Consider MISA bit choice in implied rule > * Fix the za64rs priv spec requirements > * Enable Bit Manip for OpenTitan Ibex CPU > * Fix the group bit setting of AIA with KVM > * Stop timer with infinite timecmp > * Add 'fcsr' register to QEMU log as a part of F extension > * Fix riscv64 build on musl libc > * Add preliminary textra trigger CSR functions > * RISC-V bsd-user support > * Respect firmware ELF entry point > * Add Svvptc extension support > * Fix masking of rv32 physical address > * Fix linking problem with semihosting disabled > * Fix IMSIC interrupt state updates Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2 for any user-visible changes. -- PMM
The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855: Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into staging (2024-10-01 11:34:07 +0100) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241002 for you to fetch changes up to 74b493244d0624afed22606e76fc7fca62777401: bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files (2024-10-02 15:11:52 +1000) ---------------------------------------------------------------- RISC-V PR for 9.2 * Add a property to set vl to ceil(AVL/2) * Enable numamem testing for RISC-V * Consider MISA bit choice in implied rule * Fix the za64rs priv spec requirements * Enable Bit Manip for OpenTitan Ibex CPU * Fix the group bit setting of AIA with KVM * Stop timer with infinite timecmp * Add 'fcsr' register to QEMU log as a part of F extension * Fix riscv64 build on musl libc * Add preliminary textra trigger CSR functions * RISC-V bsd-user support * Respect firmware ELF entry point * Add Svvptc extension support * Fix masking of rv32 physical address * Fix linking problem with semihosting disabled * Fix IMSIC interrupt state updates ---------------------------------------------------------------- Alexandre Ghiti (1): target: riscv: Add Svvptc extension support Alistair Francis (1): target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target/riscv: Add textra matching condition for the triggers Andrew Jones (3): target/riscv/kvm: Fix the group bit setting of AIA target/riscv: Stop timer with infinite timecmp target/riscv32: Fix masking of physical address Daniel Henrique Barboza (1): target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Haibo Xu (3): tests/acpi: Add empty ACPI SRAT data file for RISC-V tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V tests/acpi: Add expected ACPI SRAT AML file for RISC-V Jason Chien (1): target/riscv: Add a property to set vl to ceil(AVL/2) Maria Klauchek (1): target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Implement RISC-V TLS register setup bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Define RISC-V register structures and register copying bsd-user: Add RISC-V signal trampoline setup function bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Add RISC-V thread setup and initialization support bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Define RISC-V system call structures and constants bsd-user: Define RISC-V signal handling structures and constants bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Milan P. Stanić (1): util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Samuel Holland (1): hw/riscv: Respect firmware ELF entry point Thomas Huth (1): target/riscv/cpu_helper: Fix linking problem with semihosting disabled Tomasz Jeznach (1): hw/intc: riscv-imsic: Fix interrupt state updates. Vladimir Isaev (1): target/riscv: fix za64rs enabling Warner Losh (2): bsd-user: Add generic RISC-V64 target definitions bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files configs/targets/riscv64-bsd-user.mak | 4 + bsd-user/riscv/target.h | 20 ++++ bsd-user/riscv/target_arch.h | 27 +++++ bsd-user/riscv/target_arch_cpu.h | 148 ++++++++++++++++++++++++++ bsd-user/riscv/target_arch_elf.h | 42 ++++++++ bsd-user/riscv/target_arch_reg.h | 88 ++++++++++++++++ bsd-user/riscv/target_arch_signal.h | 75 +++++++++++++ bsd-user/riscv/target_arch_sigtramp.h | 41 +++++++ bsd-user/riscv/target_arch_sysarch.h | 41 +++++++ bsd-user/riscv/target_arch_thread.h | 47 +++++++++ bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++++ bsd-user/riscv/target_syscall.h | 38 +++++++ include/hw/riscv/boot.h | 4 +- target/riscv/cpu_bits.h | 10 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/debug.h | 3 + bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++++++ bsd-user/riscv/target_arch_cpu.c | 29 +++++ hw/intc/riscv_imsic.c | 50 +++++---- hw/riscv/boot.c | 11 +- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/opentitan.c | 3 +- hw/riscv/shakti_c.c | 13 ++- hw/riscv/sifive_u.c | 4 +- hw/riscv/spike.c | 5 +- hw/riscv/virt.c | 4 +- target/riscv/cpu.c | 16 ++- target/riscv/cpu_helper.c | 8 +- target/riscv/debug.c | 114 ++++++++++++++++++-- target/riscv/kvm/kvm-cpu.c | 4 +- target/riscv/tcg/tcg-cpu.c | 13 ++- target/riscv/time_helper.c | 1 + target/riscv/vector_helper.c | 2 + tests/qtest/bios-tables-test.c | 28 +++++ util/cpuinfo-riscv.c | 1 + target/riscv/Kconfig | 4 +- tests/data/acpi/riscv64/virt/SRAT.numamem | Bin 0 -> 108 bytes 37 files changed, 1068 insertions(+), 57 deletions(-) create mode 100644 configs/targets/riscv64-bsd-user.mak create mode 100644 bsd-user/riscv/target.h create mode 100644 bsd-user/riscv/target_arch.h create mode 100644 bsd-user/riscv/target_arch_cpu.h create mode 100644 bsd-user/riscv/target_arch_elf.h create mode 100644 bsd-user/riscv/target_arch_reg.h create mode 100644 bsd-user/riscv/target_arch_signal.h create mode 100644 bsd-user/riscv/target_arch_sigtramp.h create mode 100644 bsd-user/riscv/target_arch_sysarch.h create mode 100644 bsd-user/riscv/target_arch_thread.h create mode 100644 bsd-user/riscv/target_arch_vmparam.h create mode 100644 bsd-user/riscv/target_syscall.h create mode 100644 bsd-user/riscv/signal.c create mode 100644 bsd-user/riscv/target_arch_cpu.c create mode 100644 tests/data/acpi/riscv64/virt/SRAT.numamem