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Update the corresponding masks accordingly. [1]https://github.com/riscv/riscv-isa-manual/issues/1578 Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7e3f629356ba..a7b8bcbd0148 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -938,8 +938,8 @@ typedef enum RISCVException { MHPMEVENTH_BIT_VSINH | \ MHPMEVENTH_BIT_VUINH) -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) -#define MHPMEVENT_IDX_MASK 0xFFFFF +#define MHPMEVENT_SSCOF_MASK 0xFF00000000000000ULL +#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK) #define MHPMEVENT_SSCOF_RESVD 16 /* JVT CSR bits */