| Message ID | 20241010111822.345-6-alireza.sanaee@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Specifying cache topology on ARM | expand |
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 36e5c0adde..65219f8823 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2020,6 +2020,10 @@ static void test_acpi_aarch64_virt_tcg_topology(void) }; test_acpi_one("-cpu cortex-a57 " + "-M smp-cache.0.cache=l1i,smp-cache.0.topology=cluster," + "smp-cache.1.cache=l1d,smp-cache.1.topology=cluster," + "smp-cache.2.cache=l2,smp-cache.2.topology=cluster," + "smp-cache.3.cache=l3,smp-cache.3.topology=cluster " "-smp sockets=1,clusters=2,cores=2,threads=2", &data); free_test_data(&data); }
Test new PPTT topolopy with cache representation. Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> --- tests/qtest/bios-tables-test.c | 4 ++++ 1 file changed, 4 insertions(+)