Message ID | 20241017174409.832033-1-pbonzini@redhat.com (mailing list archive) |
---|---|
State | New |
Headers | show |
On Thu, 17 Oct 2024 at 18:45, Paolo Bonzini <pbonzini@redhat.com> wrote: > > The following changes since commit f774a677507966222624a9b2859f06ede7608100: > > Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-10-15 15:18:22 +0100) > > are available in the Git repository at: > > https://gitlab.com/bonzini/qemu.git tags/for-upstream > > for you to fetch changes up to 15d955975bd484c2c66af0d6daaa02a7d04d2256: > > target/i386: Use only 16 and 32-bit operands for IN/OUT (2024-10-17 19:41:30 +0200) > > ---------------------------------------------------------------- > * tcg/s390x: Fix for TSTEQ/TSTNE > * target/i386: Fixes for IN and OUT with REX prefix > * target/i386: New CPUID features and logic fixes > * target/i386: Add support save/load HWCR MSR > * target/i386: Move more instructions to new decoder; separate decoding > and IR generation > * target/i386/tcg: Use DPL-level accesses for interrupts and call gates > * accel/kvm: perform capability checks on VM file descriptor when necessary > * accel/kvm: dynamically sized kvm memslots array > * target/i386: fixes for Hyper-V > * docs/system: Add recommendations to Hyper-V enlightenments doc > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2 for any user-visible changes. -- PMM
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a5d57197a4b..27bccc14e50 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -565,6 +565,20 @@ static bool tcg_target_const_match(int64_t val, int ct, } if (ct & TCG_CT_CONST_CMP) { + if (is_tst_cond(cond)) { + if (is_const_p16(uval) >= 0) { + return true; /* TMxx */ + } + if (risbg_mask(uval)) { + return true; /* RISBG */ + } + return false; + } + + if (type == TCG_TYPE_I32) { + return true; + } + switch (cond) { case TCG_COND_EQ: case TCG_COND_NE: @@ -584,13 +598,7 @@ static bool tcg_target_const_match(int64_t val, int ct, break; case TCG_COND_TSTNE: case TCG_COND_TSTEQ: - if (is_const_p16(uval) >= 0) { - return true; /* TMxx */ - } - if (risbg_mask(uval)) { - return true; /* RISBG */ - } - break; + /* checked above, fallthru */ default: g_assert_not_reached(); } @@ -3231,9 +3239,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + return C_O1_I2(r, r, ri); case INDEX_op_setcond_i32: case INDEX_op_negsetcond_i32: - return C_O1_I2(r, r, ri); case INDEX_op_setcond_i64: case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rC);